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Author SHA1 Message Date
yanming d37e92610d [VENTUS][RISCV] Remove redundant code and enable regext insertion pass when verify machineinstrs. 2023-07-07 17:08:42 +08:00
zhoujing 7da8486eb3 [VENTUS][RISCV][feat] Add data structure interface for collecting ventus program information 2023-07-07 15:42:25 +08:00
zhoujing 4fea917aec [VENTUS][RISCV][fix] Fix pattern match errors 2023-07-07 13:48:55 +08:00
yanming c0b7829a87 [VENTUS][RISCV] Skip TargetOpcode::KILL instruction in regext insertion pass. 2023-07-07 13:46:12 +08:00
yanming f5df45650f [VENTUS][RISCV] Fix private memory load/store instructions definitions. 2023-07-07 11:12:24 +08:00
yanming e2ef54c16b [VENTUS][RISCV] Fix rd,rs1,rs2,rs3 register ordering in regext insertion pass. 
Summary: Encoding register ordering in tablegen.

Test Plan: llvm/test/CodeGen/RISCV/VentusGPGPU/builtin-noverify.ll

Reviewers: zhoujing, hualin

Reviewed By: zhoujing

Differential Revision: http://www.tpt.com/D638
 2023-07-06 11:47:34 +08:00
yanming 4a12b19a74 Revert "Fix vlw12/vsw12 assembly code generation bugs * Before: vsw12.v v1, zero(v0) * After: vsw12.v v1, 0(v0)" 
This reverts commit 625746818d.
 2023-07-03 11:58:37 +08:00
yanming db2c4417fb [VENTUS][RISC][NFC] Use getAnalysis to get MachinePostDominatorTree. 2023-07-03 10:33:45 +08:00
yanming 41564530d5 [VENTUS][RISCV][Fix] Add PseudoBR when converge return bb in InsertJoinToVBranch pass. 2023-06-30 12:21:50 +08:00
yanming fe3244b577 [VENTUS][RISCV] Fix a bug in InsertJoinToVBranch pass. 2023-06-30 11:45:23 +08:00
yanming a5c8b18ce3 [VENTUS][RISCV] Fix setrpc instruction definition, use auipc + setrpc to set rpc. 
It is able to solve address ranges to [-2^31, 2^31).
 2023-06-30 11:26:58 +08:00
zhoujing 56fe569090 [VENTUS][RISCV][NFC] Disable conversion for floating VV instrcution convertion 
The copy is desired to be from GPRF32, but all the cases are from GPR, so we
disable related instruction conversion
 2023-06-29 14:28:02 +08:00
zhoujing 24dbcd9b0e [VENTUS][RISCV][NFC] Define interfaces for VENTUS 
Our previous design has two stacks, TP&SP, but we only need to store ra to sp,
and restore it from sp, this make it inconvenient to calculate stack offset for
two stack frame offset,  Here we just define interfaces, but we do not really
implement it, if needed, we need to remove callee saved registers, and modify
the related overrided functions
 2023-06-28 11:19:29 +08:00
yanming 137ae78ebe [VENTUS][RISCV] Move VentusRegextInsertionPass and VentusInsertJoinToVBranchPass before BranchRelaxationPass. 2023-06-28 11:04:47 +08:00
yanming 81c652183c [VENTUS][RISCV][fix] Delete source pseudo instruction in expandBarrier. 2023-06-27 16:27:11 +08:00
yanming 5ceac7f7a1 [VENTUS][RISCV] Fix insert setrpc/join instruction pass for VBranch. 2023-06-27 16:02:01 +08:00
zhoujing bfed578a87 [VENTUS][RISCV][fix] Fix illegal vmv instruction in libclc library 
Other than atomic functions library, there are no illegal instructions

Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-06-27 15:53:51 +08:00
yanming 7f38ea8deb [VENTUS][RISCV] Clean divergent branch analysis. 2023-06-27 14:21:24 +08:00
zhoujing d48134f86e [VENTUS][RISCV][fix] Add divergent analysis for function arguments 2023-06-27 11:44:50 +08:00
yanming 58ce5c83b8 [VENTUS][RISCV] Fix VBranch instruction info and select codegen patterns. 2023-06-27 11:12:37 +08:00
yanming df97b38340 [Ventus][RISCV] Disable insert join instruction pass. 2023-06-27 10:08:02 +08:00
zhoujing 1110ae0242 [VENTUS][RISCV][fix] Fix illegal vmv instruction for ISD::SRL SDNode 
Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-06-26 22:08:25 +08:00
yanming 6189c2e9e7 [VENTUS][RISCV] Add SETRPC and JOIN instruction definition. 2023-06-26 15:40:37 +08:00
zhoujing 14e9011074 [VENTUS][RISCV][fix] Add divergent pattern for floating instructions 
We just simply add zfinx support for floating instrionctions before,
now we add divergent analysis here to avoid illegal VGPR move to GPRF32
 2023-06-26 15:09:14 +08:00
zhoujing 7b8402802a [VENTUS][RISCV][fix] Fix calling convention 2023-06-25 22:03:04 +08:00
zhoujing f494e20d44 [VENTUS][RISCV][fix] Fix private memory access instructions' codegen errors 
We changed the private memory access' encoding in this commit `6da666856b`,
this commit is to fix the codegen bugs by that commit
 2023-06-25 10:59:21 +08:00
Aries e6b7935c89 [Ventus] ABI and stack adjustment. 
Remove all SGPRs(except ra) from callee saved register set, as they are mainly used in kernel function.
Unify the stack to use TP only, we will emit customized instructions for SP use which should not be
considered as stack according to LLVM codegen infrastructure(only 1 stack is allowed).
By unifying the stack to TP based, it is much easiler for the backend codegen.
 2023-06-21 13:08:02 +08:00
zhoujing a6e8ff959a [VENTUS][RISCV][fix] Add missing flags for building libclc 
The flags information are lost by previous merge commit `Merge libclc-vector-support`
 2023-06-21 10:59:48 +08:00
zhoujing 384651ceac [VENTUS][RISCV][fix] Fix vsetvli instruction's encoding 2023-06-21 10:16:03 +08:00
zhoujing 615705a6c6 [VENTUS][RISCV][fix] Fix calling convention 2023-06-19 17:21:04 +08:00
Aries a7b9ee473b [NFC] Fix comment style 2023-06-19 13:14:31 +08:00
Aries 6da666856b [Ventus] Fix design bug, redesign vlw.v/vsw.v to use vGPR as base address instead of using sGPR. 2023-06-19 12:59:43 +08:00
zhoujingya b438e64b66 Merge branch 'dev-ventus' 2023-06-16 17:51:00 +08:00
zhoujing 513412bb33 [VENTUS][RISCV][fix] Fix building libclc errors 2023-06-16 17:42:22 +08:00
yanming 6b0a28390e [VENTUS][RISCV][fix] Fix build warning 2023-06-16 10:25:02 +08:00
zhoujing 6636793f64 Merge libclc-vector-support 2023-06-16 09:41:08 +08:00
zhoujing 2c5cbdd187 [VENTUS][RISCV][fix] Add more divergence ananlysis 
Referenced from AMDGPU
 2023-06-15 22:34:40 +08:00
zhoujing c30c837caa [VENTUS][RISCV][fix] Fix SP stack size calculation error 2023-06-15 18:12:34 +08:00
zhoujing e54daab265 [VENTUS][RISCV][fix] Fix function call calling convention 2023-06-15 13:36:12 +08:00
zhoujing e10ff3b94d Merge branch 'main' into dev-ventus 2023-06-15 12:19:17 +08:00
Aries bc5d0f6024 Avoiding generating VGPR to SGPR copy for CopyFromReg. 2023-06-15 09:30:22 +08:00
zhoujing 53a932e665 [VENTUS][RISCV][fix] Modify calling convention for non-kernel function arguments based on private memory address 
In our previous calling convention design, all non-kernel arguments are passed
by VGPRS or TP stack, but when the arguments point to private memory address
space, the wrong memory access instructions will be generated, because private
memory based address is scalar register
 2023-06-14 21:26:53 +08:00
zhoujing 70ca64bbc8 [VENTUS][RISCV][fix] Add more load/store opcode for stack spill action 2023-06-14 11:12:37 +08:00
zhoujing e5e7a0047a [VENTUS][RISCV][fix] Fix local memory access error in kernel function 2023-06-12 16:22:45 +08:00
zhoujing 940da111a3 [VENTUS][RISCV][fix] Fix divergent analysis bug for store node 2023-06-12 14:50:55 +08:00
zhoujing c60810b243 [VENTUS][RISCV][feat] Modify SP stack size calculation 
Add initial SP stack size calculation support, still remains many issues
 2023-06-12 13:27:55 +08:00
zhoujing faf6a0bcd9 [VENTUS][RISCV][fix] Add initial Tp stack size calculation 
Cause there are two stacks in Ventus, we need to seperate TP stack and SP stack,
this commit just add very initial support for TP stack size calculation
 2023-06-11 12:18:39 +08:00
zhoujing 180b3d4429 [VENTUS][RISCV][feat] Add VGPRSpill stack id for ventus 
There are two stacks in ventus for registers spill, SGPRSpill and VGPRSpill,
SGPRSpill is for global/constant memory related GPR registers spill, VGPRSpill
is for private/shared memory related VGPR registers spill
 2023-06-07 11:57:20 +08:00
zhoujing 033505de1d [VENTUS][RISCV][fix] Modify calling convention 2023-06-05 17:11:25 +08:00
zhoujing 967cb725c8 [VENTUS][RISCV][feat] Set ventus kernel for OpenCL kernel functions 2023-06-05 13:10:35 +08:00
zhoujing 8e86eb368c [VENTUS][RISCV][workflow] Modify workflow script 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-31 12:03:02 +08:00
zhoujing 7d66e05b28 [VENTUS][RISCV][fix] Fix insert join instructions pass bug 
After this fix, the vbeq/join instructions codegen are normal now

Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-31 12:02:27 +08:00
zhoujing 8c7f5a3c28 [VENTUS][RISCV][fix] Fix instructuions which contain 5 bits unsigned immediate asmParser && pattern bug 2023-05-26 17:52:36 +08:00
zhoujing b22d7bd36f [VENTUS][RISCV][fix] Fix vlw/vsw instructions' pattern 2023-05-26 11:12:48 +08:00
zhoujing a17f01270b [VENTUS][RISCV][fix] Fix vlw12.v/vsw12.v instructions' codegen pattern 
Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-05-25 14:49:48 +08:00
zhoujingya ad23baaa51 [VENTUS][RISCV][feat] Add more floating point instructions pattern 
Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-05-25 14:48:30 +08:00
zhoujing 5d29133ab0 [VENTUS][RISCV][fix] Add isReturn block check before insertation 2023-05-25 14:09:12 +08:00
zhoujingya c0cdbbc172 [VENTUS][RISCV][style] Formatting && Change function and variable names 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-12 17:41:45 +08:00
zhoujingya 961d5a6b42 [VENTUS][RISCV][fix] Uncomment missing assertation 2023-05-12 14:46:27 +08:00
zhoujingya 97a3f99e4c [VENTUS][RISCV][pass] Add insert join instruction pass for VBranch 
we follow the following rules to insert join block and join instruction

 1: Legalize all the return block
    when there are one more return blocks in machine function, there must be
    branches, we need to reduce return blocks number down to 1
 1.1: If two return blocks have common nearest parent branch, this two blocks
    need to be joined, and we add a hasBeenJoined marker for this parent
    branch
 1.2: after we complete 1.1 process, there maybe one more return blocks, we
    need to further add join block, we recursively build dominator tree for
    these return blocks, first we find the nearest common dominator branch for
    two return blocks, and then get dominator tree path between dominator
    and each return block, we need to check this path in which whether any
    other branch blocks exists, ideally, the branch block in path should have
    been joined and marked, if not, this path is illegal, these two block can
    not be joined

 2: Insert join instructions
 2.1: we scan through the MachineBasic blocks and check what blocks to insert
    join instruction, below MBB represents MachineBasic Block
 2.2: The MBB must have one more predecessors and its nearest dominator must
     be a VBranch
 2.3: Then we analyze the the predecessor of MBB, if the predecessor
    has single successor, we add a join instruction to the predecessor end,
    other wise, we need to insert a join block between predecessor and MBB
 2023-05-12 14:01:57 +08:00
zhoujingya 5f776bde21 [VENTUS][RISCV][fix] Constraint divergent private load/store instructions can only use tp register 2023-04-27 09:32:25 +08:00
zhoujingya ea75d078fb [VENTUS][RISCV][feat] Add zfinx support 
Because there is no `F` extension and float registers in ventus, we need to
support `zfinx` to generate common float instructions
 2023-04-23 11:29:09 +08:00
zhoujingya 9d9283fa7b [VENTUS][RISCV][fix] Fix ventus abi and calling convention 
Kernel functions use sp as GPRs spill stack slots
Non-kernel functions use tp as VGPRs spill stack slots
 2023-04-20 15:27:52 +08:00
zhoujingya f28e6c5e38 [VENTUS][RISCV][feat] Add vararg backend support in ventus 
We adjust the stack growing direction early months for OpenCL, in order to be
compatible with current architecture, we need to do some modification to
support vararg
 2023-04-18 10:03:53 +08:00
zhoujingya b01963690d [VENTUS][RISCV][fix] Fix vsw/vlw encoding bugs and update test cases 
Fix vlw/vsw instructions' encoding since them have been updated
 2023-04-17 18:07:33 +08:00
zhoujingya 8ba248d102 [VENTUS][RISCV] Add vararg support 
Because ventus riscv is designed specially for OpenCL language, we originally add or remove some language features mainly for serving OpenCL, but we now need to add customized `printf` function which is expected to be written in C, so we need also to add support for C language features in current ventus

Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-04-13 15:00:35 +08:00
zhoujingya 458808b5d1 Remove FeatureStdExtC in ventus 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-03-30 10:14:52 +08:00
zhoujingya 625746818d Fix vlw12/vsw12 assembly code generation bugs * Before: vsw12.v v1, zero(v0) * After: vsw12.v v1, 0(v0) 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-03-28 13:49:47 +08:00
zhoujingya 2b54041ac3 Fix encoding bug for endprg&vmx.v.x&barrier 2023-03-27 17:44:38 +08:00
zhoujingya 6f45d90f90 Update vlw12/vsw12 instructions' encoding 2023-03-23 17:21:38 +08:00
zhoujingya 94597a71ad Fix the encoding bug of barrier 2023-03-22 17:55:22 +08:00
zhoujingya 53c8b524e8 Add vsetvli instruction to support spike 2023-03-21 15:48:54 +08:00
zhoujingya dfc6b4d7f0 Fix VI instruction codegen bug && disable declare-opencl-builtins option for opencl 2023-03-20 16:30:08 +08:00
zhoujingya 553e65dcf7 Change barrier and work_group_barrier into builtin functions 2023-03-14 10:38:22 +08:00
zhoujingya ad550a1375 Update load/store instructions pattern && add test cases for load/store codegen 2023-03-03 11:41:13 +08:00
zhoujing ff4e666b80 Fix addrRegReg bug & Add pattern for load/store 
* TODO: Need to write test files later
 2023-02-28 22:04:07 +08:00
zhoujing 60a504f481 Update customized instructions' encoding 2023-02-24 11:21:19 +08:00
zhoujing a92723f212 Update barrier intrinsics' name and modify barrier's encoding 2023-02-10 14:50:40 +08:00
zhoujing 23fe611d6e Fix barriersub instruction pattern match bug 2023-02-10 10:44:22 +08:00
zhoujing 18810a86c0 Update barrier&barriersub instructions, codegen test cases for barrier builtins and intrinsics 2023-02-10 10:27:46 +08:00
zhoujing f75aab9a57 Fix endprg's encoding and add barrier instruction 2023-02-08 11:35:57 +08:00
zhoujing 47fc50bb92 Add pass to support VX/VF instruction generation 
Summary: Add pass to support VX/VF instruction generation

Test Plan: none

Reviewers: hualin

Reviewed By: hualin

Subscribers: yanming

Differential Revision: http://www.tpt.com/D583
 2023-02-07 14:00:15 +08:00
zhoujing e74aafb0d6 Change vftta&vfexp instructions' encoding formats 2023-01-28 10:46:31 +08:00
Aries 9318d5354f [NFC] Fix coding style 2023-01-28 09:53:19 +08:00
Aries 192ee0187a [NFC] Fix coding style 2023-01-28 09:49:39 +08:00
zhoujing 93143b5b35 Add definition for vfexp/vftta 2023-01-20 09:57:19 +08:00
Aries 438f1c92c4 Fix some build warnings 2023-01-19 09:45:27 +08:00
Aries 890dddc205 Add missing C ext feature to Ventus GPGPU 2023-01-18 15:09:38 +08:00
Aries 71979c7b0d [NFC] Add comment to FLW/FSW 2023-01-18 15:09:18 +08:00
zhoujing eecbe33eb1 Fix instruction encoding conflicts 2023-01-18 11:20:14 +08:00
zhoujing 229b27b714 Update instructions for vector load/store 2023-01-17 17:46:59 +08:00
Aries 2c6aaa910c Add endprg, vid.v instruction definition 2023-01-17 14:39:57 +08:00
zhoujing 23821f9116 Change some patterns' format 2023-01-17 09:34:59 +08:00
Aries 2d601dc47f Fix bug for Ventus TTI getRegisterBitWidth 2023-01-16 16:06:53 +08:00
Aries f933867e85 Fix linking error with pocl when llvm is built as shared libraries 2023-01-16 16:03:17 +08:00
zhoujing a81a56274f Update float point instructions test case 2023-01-12 16:43:47 +08:00
zhoujing fcd285daae Modify file formats && add predicate for float point instruction 
* Based on zcc commit: 6e63555df68b5ce96d0af3dceb822abb2a2c9481
 2023-01-10 10:25:58 +08:00
zhoujing 7e701d4ba1 Add support for float point trunc instruction match 2023-01-09 18:06:39 +08:00
zhoujing 899ca9fd8e Add support for 12 bits immediate 2023-01-09 11:59:45 +08:00
zhoujing cfc9476c48 Update pattern and test cases for floating-point sign-injection Instruction 2023-01-05 17:44:06 +08:00
zhoujing 02392af08a Update pattern and test cases for float/integer arithmetic instructions 2023-01-05 13:35:58 +08:00
zhoujing c635182266 Update pattern and test cases for float/integer convert instructions 2023-01-04 15:04:36 +08:00
Aries a173844ae5 Grow Ventus GPGPU stack upwards instead of downwards 2023-01-04 10:29:53 +08:00
zhoujing eb54dc382c Update pattern for float select instructions && update test cases 2023-01-04 10:21:49 +08:00
Aries f9dd113822 Turn on ABI register naming 2023-01-03 11:36:49 +08:00
Aries 78434601d8 Generate vlw/vsw instructions for private memory access 2023-01-03 11:08:24 +08:00
Aries 0b43b70327 Fix bug in addressing space mapping 2023-01-03 10:45:58 +08:00
zhoujing dcf8ab214e Typo fixes 2022-12-30 17:25:15 +08:00
zhoujing 8f6c31ea7d Add pattern for integer select instructions 2022-12-30 16:22:59 +08:00
zhoujing 1fab7b80f3 Legalize operation for SETCC 2022-12-29 17:13:49 +08:00
Aries d6ca871320 Add 'regext' instruction definition and insertion pass. 
As the VentusRegExtInsertion pass will break the def-use chain, so it should
only run without -verify-machineinstrs and should only be run at the very end
of codegen pass.
 2022-12-29 16:53:18 +08:00
zhoujing 734f087a82 Update test cases and fix the bug of wrong move from GPR to VGPR 2022-12-29 13:46:34 +08:00
Aries 17adb707e6 Fix bug in kernel arg memory offset calculation 2022-12-29 11:53:29 +08:00
zhoujing 64b95e02f9 Add pattern for float point ternary operation and add test cases 
* fneg operation need to be added, need to define uniform pattern to simplify code
* VX instructions need to be added later
 2022-12-28 17:57:24 +08:00
Aries 9925e4e511 Define callee saved registers for Ventus GPGPU. 
Initially implemented 2 stacks support for sGPR spill/restore stack and per-thread stack,
but stack size calculation is computed as a sum of 2 stacks(this works but wastes lot of
spaces).
Now TP register is used as per-thread stack pointer, SP register is used for sGPR spill/restore.
Clean up RVV related stack frame code etc.
 2022-12-28 16:37:38 +08:00
Aries 424ea45e4f Update Ventus GPGPU ABI: X4 as stack pointer, V0-V31 as arguments registers etc 2022-12-28 13:11:22 +08:00
Aries 228be521e5 Add initial different stack frame support for sALU and vALU. 
FIXME: The stack pointer RISCV::X4 for vALU is not yet correctly used, but related infrastructure
should work(MFI.isEntryFunction() is used to check RISCV::X2 or RISCV::X4 to be used as stack pointer).
 2022-12-27 18:28:51 +08:00
Aries e8368c07e1 Fix kernel argument lowering alignment bug. 2022-12-27 17:00:46 +08:00
Aries 3a9c32a024 Add initial vector support(calling convention fix). 2022-12-27 16:35:12 +08:00
Aries da5006ca8d Add support to lowering BITCAST and Constant Pool for zfinx etc 2022-12-27 13:39:46 +08:00
Aries 9be2c54215 Add initial vGPR + sGPRF32 (zfinx) support 2022-12-27 12:00:30 +08:00
Aries 7d7ef235fd Support f32 return type in VGPR 2022-12-27 11:21:08 +08:00
Aries 7fb5ae0a92 Add very initial vALU floating point support. 2022-12-27 11:19:14 +08:00
Aries 4d387117be Add multi data type support for VGPR register class. 2022-12-27 11:01:26 +08:00
Aries c734a517f4 Fix bug in building VSUXEI32 MI for stack slot load/restore 2022-12-23 10:17:52 +08:00
Aries 67109cea5b Add LegancyDivergenceAnalysis pass as prerequisite to SelectionDAG pass. 2022-12-23 10:03:43 +08:00
Aries 1b3dcad1b5 Simple vALU branch now works. 2022-12-22 18:01:55 +08:00
Aries 2f946d86ad Fix basicblock insertion ordering for ISD::SELECT lowering. 2022-12-22 17:47:03 +08:00
Aries 73846a1613 Do not try to merge branches for vALU execution path, 
as explicit branch and join instructions are required for SIMT stack working correctly.
 2022-12-22 17:42:10 +08:00
Aries cb6f30fbd7 Add initial support to lower ISD::SELECT into branch instructions in divergent execution path. 2022-12-22 17:17:02 +08:00
Aries b9da010dd5 [NFC] Refactor messy switch...case 2022-12-22 14:50:13 +08:00
Aries 05bc6809f7 Correctly create VMV_S_X instruction to pass machine instr verification pass. 2022-12-22 11:49:07 +08:00
Aries 30b0b43676 Add basic support to select vALU load/store instruction. 2022-12-22 10:55:14 +08:00
Aries 86ffbad424 Fix vALU stack load/store instruction generation. 2022-12-22 10:21:33 +08:00
Aries 93ce3641ec Fix bug in creating sGPR to vGPR register copy instruction. 2022-12-22 09:24:18 +08:00
Aries 926e75a1f8 [WORKAROUND] Do not use ABI register name yet 2022-12-21 17:40:19 +08:00
Aries d39e0084b1 Restore code which enables MC emitter 2022-12-21 17:40:19 +08:00
Aries 8c531048c2 Initially add vector load/store instruction and related codegen 2022-12-21 16:27:39 +08:00
zhoujing e171152174 Remeve VV for vmsgtu/vmsgt 2022-12-21 09:51:37 +08:00
Aries beb878e97c Add OpenCL addressing space mapping to RISCVAS. 
Add kernel argument lowering.
Clean up a few unrelated RVV code.
 2022-12-20 17:08:08 +08:00
zhoujing e2572c660e Add VI version for vmsltu/vmslt and add VV version for vmsgt/vmsgtu 2022-12-20 13:02:36 +08:00
zhoujing 1cbcda97b8 Add pattern for VX, VI instruction and take reverse operation into account 2022-12-20 10:56:27 +08:00
Aries f53fefd983 Fix build error. Now we can have initial divergent execution code generated as expected. 2022-12-20 09:41:21 +08:00
Aries dee3135130 Drafting divergent related code, not working yet. 2022-12-19 18:11:34 +08:00
Aries 878fba7d40 Remove vmv.v{vxi} insturction which is now replaced by vmv.x.s/vmv.s.x 2022-12-19 14:25:23 +08:00
Aries c6b68cbedb Support move between vGPR and sGPR. 
Fix a few bugs in calling convention related lowering functions.
 2022-12-19 14:21:26 +08:00
Aries 4e0cd22745 Add vALU conditional branch instructions 2022-12-19 13:09:00 +08:00
Aries 894931f522 More clean up and fix build error. 2022-12-19 10:10:28 +08:00
Aries 521e83631d Roughly cleaned RVV instruction selection. 2022-12-19 09:40:05 +08:00
Aries 35633e31e3 In the middle of removing RVV code. 2022-12-16 18:04:43 +08:00