[VENTUS][RISCV][pass] Add insert join instruction pass for VBranch
we follow the following rules to insert join block and join instruction
1: Legalize all the return block
when there are one more return blocks in machine function, there must be
branches, we need to reduce return blocks number down to 1
1.1: If two return blocks have common nearest parent branch, this two blocks
need to be joined, and we add a hasBeenJoined marker for this parent
branch
1.2: after we complete 1.1 process, there maybe one more return blocks, we
need to further add join block, we recursively build dominator tree for
these return blocks, first we find the nearest common dominator branch for
two return blocks, and then get dominator tree path between dominator
and each return block, we need to check this path in which whether any
other branch blocks exists, ideally, the branch block in path should have
been joined and marked, if not, this path is illegal, these two block can
not be joined
2: Insert join instructions
2.1: we scan through the MachineBasic blocks and check what blocks to insert
join instruction, below MBB represents MachineBasic Block
2.2: The MBB must have one more predecessors and its nearest dominator must
be a VBranch
2.3: Then we analyze the the predecessor of MBB, if the predecessor
has single successor, we add a join instruction to the predecessor end,
other wise, we need to insert a join block between predecessor and MBB
This commit is contained in:
parent
a0a80bfdad
commit
97a3f99e4c
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@ -41,6 +41,7 @@ add_llvm_target(RISCVCodeGen
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RISCVTargetTransformInfo.cpp
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VentusRegextInsertion.cpp
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VentusVVInstrConversion.cpp
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VentusInsertJoinToVBranch.cpp
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GISel/RISCVCallLowering.cpp
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GISel/RISCVInstructionSelector.cpp
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GISel/RISCVLegalizerInfo.cpp
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@ -72,6 +72,9 @@ void initializeVentusRegextInsertionPass(PassRegistry &);
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FunctionPass *createVentusVVInstrConversionPass();
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void initializeVentusVVInstrConversionPass(PassRegistry &);
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FunctionPass *createVentusInsertJoinToVBranchPass();
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void initializeVentusInsertJoinToVBranchPass(PassRegistry &);
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InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
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RISCVSubtarget &,
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RISCVRegisterBankInfo &);
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@ -286,6 +286,7 @@ void RISCVPassConfig::addPreEmitPass2() {
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// Insert regext instruction for instruction whose register id is greater
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// than 31.
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addPass(createVentusRegextInsertionPass());
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addPass(createVentusInsertJoinToVBranchPass());
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}
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void RISCVPassConfig::addMachineSSAOptimization() {
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@ -302,11 +303,13 @@ void RISCVPassConfig::addPreRegAlloc() {
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if (TM->getOptLevel() != CodeGenOpt::None)
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addPass(createRISCVMergeBaseOffsetOptPass());
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addPass(createVentusVVInstrConversionPass());
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}
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void RISCVPassConfig::addPostRegAlloc() {
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if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
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addPass(createRISCVRedundantCopyEliminationPass());
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}
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yaml::MachineFunctionInfo *
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@ -0,0 +1,388 @@
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//===-- VentusInsertJoinToBranch.cpp - Insert join to VBranches -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// In Ventus, if VBranch instructions are generated, we need to insert join
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// instructions in both `else` and `then` branch to tell hardware where these
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// two branches need to join together
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//
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// we follow the following rules to insert join block and join instruction
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//
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// 1: Legalize all the return block
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// when there are one more return blocks in machine function, there must be
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// branches, we need to reduce return blocks number down to 1
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// 1.1: If two return blocks have common nearest parent branch, this two blocks
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// need to be joined, and we add a hasBeenJoined marker for this parent
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// branch
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// 1.2: after we complete 1.1 process, there maybe one more return blocks, we
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// need to further add join block, we recursively build dominator tree for
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// these return blocks, first we find the nearest common dominator branch for
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// two return blocks, and then get dominator tree path between dominator
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// and each return block, we need to check this path in which whether any
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// other branch blocks exists, ideally, the branch block in path should have
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// been joined and marked, if not, this path is illegal, these two block can
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// not be joined
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//
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// 2: Insert join instructions
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// 2.1: we scan through the MachineBasic blocks and check what blocks to insert
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// join instruction, below MBB represents MachineBasic Block
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// 2.2: The MBB must have one more predecessors and its nearest dominator must
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// be a VBranch
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// 2.3: Then we analyze the the predecessor of MBB, if the predecessor
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// has single successor, we add a join instruction to the predecessor end,
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// other wise, we need to insert a join block between predecessor and MBB
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVInstrInfo.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/CodeGenPassBuilder.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#define VENTUS_INSERT_JOIN_TO_BRANCH "Insert join to VBranch"
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#define DEBUG_TYPE "Insert_join_to_VBranch"
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using namespace llvm;
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namespace {
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struct BranchInfo {
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bool isDivergentBranch = false; // MBB is divergent branch or not
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bool hasBeenJoined = false; // MBB has been joined
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};
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class VentusInsertJoinToVBranch : public MachineFunctionPass {
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public:
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const RISCVInstrInfo *TII;
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static char ID;
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MachineFunction *MachineFunc;
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const RISCVRegisterInfo *MRI;
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const MachineRegisterInfo *MR;
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SmallVector<MachineBasicBlock *, 8> ReturnBlock;
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SmallDenseMap<MachineBasicBlock *, BranchInfo> BranchMBBInfo;
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MachineDominatorTree *MDT = new MachineDominatorTree();
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VentusInsertJoinToVBranch() : MachineFunctionPass(ID) {
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initializeVentusInsertJoinToVBranchPass(*PassRegistry::getPassRegistry());
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}
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~VentusInsertJoinToVBranch() { delete MDT; }
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// Collect all the branch blocks information in function
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void collectBranchMBBInfo(MachineFunction &MF);
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bool insertJoinMBB(MachineBasicBlock &MBB1, MachineBasicBlock &MBB2);
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bool runOnMachineFunction(MachineFunction &MF) override;
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bool legalizeRetMBB(MachineBasicBlock &MBB);
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bool hasCommonNearestParentBranch(MachineBasicBlock &MBB1,
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MachineBasicBlock &MBB2);
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bool canJoinMBB(MachineBasicBlock &MBB1, MachineBasicBlock &MBB2);
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/// This function check two return blocks whether can join or not
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bool hasNoUnjoinedBranch(MachineBasicBlock *CurrMBB,
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MachineBasicBlock *TargetMBB);
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/// Find all the branch predecessor no matter direct or indirect
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SmallVector<MachineBasicBlock *>
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findAllNearestParentBranches(MachineBasicBlock &MBB);
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/// Check MBB is divergent branch or not
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bool isDivergentBranchBlock(MachineBasicBlock &MBB) {
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if (MBB.empty())
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return false;
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const MachineInstr &MI = MBB.instr_back();
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switch (MI.getOpcode()) {
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default:
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return false;
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case RISCV::VBEQ:
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case RISCV::VBNE:
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case RISCV::VBLT:
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case RISCV::VBGE:
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case RISCV::VBLTU:
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case RISCV::VBGEU:
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return true;
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}
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}
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/// Check MBB is common branch or not
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bool isCommonBranchBlock(MachineBasicBlock &MBB) {
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if (MBB.empty())
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return false;
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const MachineInstr &MI = MBB.instr_back();
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switch (MI.getOpcode()) {
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default:
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return false;
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case RISCV::BEQ:
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case RISCV::BNE:
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case RISCV::BLT:
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case RISCV::BGE:
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case RISCV::BLTU:
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case RISCV::BGEU:
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return true;
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}
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}
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// virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
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// AU.addRequired<BranchFolderPass>();
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// AU.setPreservesAll();
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// }
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/// Legalize all the return MBB
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bool canJoinRetMBB(MachineFunction &MF);
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/// Get return MBB numbers
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unsigned getReturnBlockNum(MachineFunction &MF);
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StringRef getPassName() const override {
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return VENTUS_INSERT_JOIN_TO_BRANCH;
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}
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};
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char VentusInsertJoinToVBranch::ID = 0;
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void VentusInsertJoinToVBranch::collectBranchMBBInfo(MachineFunction &MF) {
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for (auto &MBB : MF) {
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if (isCommonBranchBlock(MBB))
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BranchMBBInfo[&MBB] = {false, false};
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else if (isDivergentBranchBlock(MBB))
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BranchMBBInfo[&MBB] = {true, false};
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}
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}
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unsigned VentusInsertJoinToVBranch::getReturnBlockNum(MachineFunction &MF) {
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// Clear return block before each analysis
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if (!ReturnBlock.empty())
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ReturnBlock.clear();
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unsigned ReturnBlockNum = 0;
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for (auto &MBB : MF) {
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if (MBB.isReturnBlock()) {
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// Original return blocks
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ReturnBlock.push_back(&MBB);
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ReturnBlockNum++;
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}
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}
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return ReturnBlockNum;
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}
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bool VentusInsertJoinToVBranch::insertJoinMBB(MachineBasicBlock &MBB1,
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MachineBasicBlock &MBB2) {
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MachineBasicBlock *PseudoJoinMBB = MachineFunc->CreateMachineBasicBlock();
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BuildMI(*PseudoJoinMBB, PseudoJoinMBB->end(), DebugLoc(),
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TII->get(RISCV::PseudoRET));
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MachineFunc->push_back(PseudoJoinMBB);
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legalizeRetMBB(MBB1);
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legalizeRetMBB(MBB2);
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MBB1.addSuccessor(PseudoJoinMBB);
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MBB2.addSuccessor(PseudoJoinMBB);
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return true;
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}
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/// Check if two return blocks can join or not
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bool VentusInsertJoinToVBranch::canJoinMBB(MachineBasicBlock &MBB1,
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MachineBasicBlock &MBB2) {
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auto DominatorBlock = MDT->findNearestCommonDominator(&MBB1, &MBB2);
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if (DominatorBlock) {
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if (!hasNoUnjoinedBranch(DominatorBlock, &MBB1) &&
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!hasNoUnjoinedBranch(DominatorBlock, &MBB2)) {
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BranchMBBInfo.find(DominatorBlock)->second.hasBeenJoined = true;
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return true;
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}
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}
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return false;
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}
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bool VentusInsertJoinToVBranch::runOnMachineFunction(MachineFunction &MF) {
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bool IsChanged = false;
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TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
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MRI = MF.getSubtarget<RISCVSubtarget>().getRegisterInfo();
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MR = &MF.getRegInfo();
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MachineFunc = &MF;
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collectBranchMBBInfo(MF);
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MDT->getBase().recalculate(*MachineFunc);
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// After this check, all return blocks are expected to be legal
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IsChanged |= canJoinRetMBB(MF);
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MDT->getBase().recalculate(*MachineFunc);
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// assert(getReturnBlockNum(MF) == 1 && "Join return MBB process not
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// completed");
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for (auto &MBB : make_early_inc_range(MF)) {
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MachineDomTreeNode *Node = MDT->getNode(&MBB);
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if (Node && Node->getIDom()) {
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// At least two predecessors
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unsigned PredecessorNum = std::distance(MBB.pred_begin(), MBB.pred_end());
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if (BranchMBBInfo.find(Node->getIDom()->getBlock()) !=
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BranchMBBInfo.end() &&
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BranchMBBInfo.find(Node->getIDom()->getBlock())
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->getSecond()
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.isDivergentBranch &&
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PredecessorNum > 1) {
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SmallVector<MachineBasicBlock *, 4> Predecessors;
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for (auto Pred : MBB.predecessors())
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Predecessors.push_back(Pred);
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for (auto Predecessor : make_early_inc_range(Predecessors)) {
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// Divergent branch, insert a block between MBB & predecessor
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if (isDivergentBranchBlock(*Predecessor)) {
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MachineBasicBlock *NewBB = MF.CreateMachineBasicBlock();
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// This is essential to keep CFG legal, if MBB is the fall through
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// block of predecessor, the NewBB should replace MBB's place
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// otherwise, we only need to insert before MBB
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if (Predecessor->getFallThrough() == &MBB)
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MF.insert(std::next(Predecessor->getIterator()), NewBB);
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else
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MF.insert(MBB.getIterator(), NewBB);
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Predecessor->replaceSuccessor(&MBB, NewBB);
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NewBB->addSuccessor(&MBB);
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BuildMI(*NewBB, NewBB->end(), DebugLoc(), TII->get(RISCV::JOIN))
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.addMBB(&MBB);
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MachineInstr *LastInst = &(*Predecessor->getFirstInstrTerminator());
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assert(LastInst->isBranch() && "Not branch instruction");
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LastInst->getOperand(2).setMBB(NewBB);
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} else {
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// Avoid duplicate JOIN add
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if (!(Predecessor->instr_back().getOpcode() == RISCV::JOIN))
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BuildMI(*Predecessor, Predecessor->end(), DebugLoc(),
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TII->get(RISCV::JOIN))
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.addMBB(&MBB);
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}
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}
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}
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}
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}
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return IsChanged;
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}
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bool VentusInsertJoinToVBranch::canJoinRetMBB(MachineFunction &MF) {
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bool IsChanged = false;
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// Check two MBBs' nearest parent branch MBB is the same or not, if is same
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// we need to join them to a maybe Joint block. otherwise
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unsigned ReturnBlockNum = getReturnBlockNum(MF);
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for (size_t i = 0; i < ReturnBlockNum; i++) {
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for (size_t j = i + 1; j < ReturnBlockNum; j++) {
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if (hasCommonNearestParentBranch(*ReturnBlock[i], *ReturnBlock[j]))
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IsChanged |= insertJoinMBB(*ReturnBlock[i], *ReturnBlock[j]);
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}
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}
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// Rebuild dominator tree
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MDT->getBase().recalculate(MF);
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unsigned RetNum = getReturnBlockNum(MF);
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while (true) {
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for (size_t i = 0; i < ReturnBlock.size(); i++) {
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for (size_t j = i + 1; j < ReturnBlock.size(); j++) {
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if (canJoinMBB(*ReturnBlock[i], *ReturnBlock[j]))
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IsChanged |= insertJoinMBB(*ReturnBlock[i], *ReturnBlock[j]);
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}
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}
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// After check, rebuild dominator tree
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MDT->getBase().recalculate(MF);
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unsigned RetNum1 = getReturnBlockNum(MF);
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if (RetNum1 == RetNum)
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// Avoid dead loop
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break;
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RetNum = RetNum1;
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}
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return IsChanged;
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}
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/// Legalize return block, right now, we only consider tail call && ret
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bool VentusInsertJoinToVBranch::legalizeRetMBB(MachineBasicBlock &MBB) {
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// Get last instruction in this basic block
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if (MBB.empty())
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return false;
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MachineInstr *LastInst = &(*MBB.instr_rbegin());
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unsigned LastInstOpcode = LastInst->getOpcode();
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assert(LastInstOpcode == RISCV::PseudoRET ||
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LastInstOpcode == RISCV::PseudoTAIL && "Unexpected opcode");
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// If opcode is RISCV::PseudoRET, keep a copy of this instruction
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if (LastInstOpcode == RISCV::PseudoRET)
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// Get the return instruction's implicit operands
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LastInst->eraseFromParent();
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else
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LastInst->setDesc(TII->get(RISCV::PseudoCALL));
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return true;
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}
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bool VentusInsertJoinToVBranch::hasCommonNearestParentBranch(
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MachineBasicBlock &MBB1, MachineBasicBlock &MBB2) {
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auto ParentBranches1 = findAllNearestParentBranches(MBB1);
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auto ParentBranches2 = findAllNearestParentBranches(MBB2);
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for (auto Branch : ParentBranches1) {
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if (std::find(ParentBranches2.begin(), ParentBranches2.end(), Branch) !=
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ParentBranches2.end()) {
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auto BranchMBB =
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std::find(ParentBranches2.begin(), ParentBranches2.end(), Branch);
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if (BranchMBBInfo.find(*BranchMBB) != BranchMBBInfo.end())
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// Update BranchMBB's hasBeenJoined flag
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BranchMBBInfo.find(*BranchMBB)->getSecond().hasBeenJoined = true;
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return true;
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}
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}
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return false;
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}
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SmallVector<MachineBasicBlock *>
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VentusInsertJoinToVBranch::findAllNearestParentBranches(
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MachineBasicBlock &MBB) {
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SmallVector<MachineBasicBlock *, 8> BranchParents;
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for (auto Pred : MBB.predecessors()) {
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unsigned PredNum = std::distance(Pred->succ_begin(), Pred->succ_end());
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if (PredNum >= 2)
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BranchParents.push_back(Pred);
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else {
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auto Parents = findAllNearestParentBranches(*Pred);
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BranchParents.insert(BranchParents.end(), Parents.begin(), Parents.end());
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}
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}
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return BranchParents;
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}
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bool VentusInsertJoinToVBranch::hasNoUnjoinedBranch(
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MachineBasicBlock *DominatorMBB, MachineBasicBlock *TargetMBB) {
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// Find the path between MBB1 and its immediate dominator
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MachineDomTreeNode *TargetMBBNode = MDT->getNode(TargetMBB);
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SmallVector<MachineBasicBlock *, 4> Path;
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// Build path between dominator DominatorMBB and TargetMBB
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// FIXME: Maybe can simplify below codes
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while (TargetMBBNode && TargetMBBNode->getBlock() != DominatorMBB &&
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TargetMBBNode->getIDom()->getBlock() != DominatorMBB) {
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Path.push_back(TargetMBBNode->getBlock());
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TargetMBBNode = TargetMBBNode->getIDom();
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}
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// Traverse this path, if found unjoined branch, return true
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for (auto path : Path) {
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if (BranchMBBInfo.find(path) != BranchMBBInfo.end()) {
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if (!BranchMBBInfo.find(path)->getSecond().hasBeenJoined)
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return true;
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}
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}
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return false;
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}
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} // end of anonymous namespace
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INITIALIZE_PASS(VentusInsertJoinToVBranch, "Insert-join-to-VBranch",
|
||||
VENTUS_INSERT_JOIN_TO_BRANCH, false, false)
|
||||
|
||||
namespace llvm {
|
||||
FunctionPass *createVentusInsertJoinToVBranchPass() {
|
||||
return new VentusInsertJoinToVBranch();
|
||||
}
|
||||
} // end of namespace llvm
|
||||
|
|
@ -0,0 +1,395 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mcpu=ventus-gpgpu -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=VENTUS %s
|
||||
|
||||
; Function Attrs: convergent mustprogress nofree norecurse nounwind willreturn memory(none) vscale_range(1,2048)
|
||||
define dso_local i32 @branch(i32 noundef %dim) local_unnamed_addr {
|
||||
; VENTUS-LABEL: branch:
|
||||
; VENTUS: # %bb.0: # %entry
|
||||
; VENTUS-NEXT: addi tp, tp, 16
|
||||
; VENTUS-NEXT: .cfi_def_cfa_offset 16
|
||||
; VENTUS-NEXT: sw ra, -16(sp) # 4-byte Folded Spill
|
||||
; VENTUS-NEXT: .cfi_offset ra, 0
|
||||
; VENTUS-NEXT: vmv.v.x v0, zero
|
||||
; VENTUS-NEXT: call _Z13get_global_idj
|
||||
; VENTUS-NEXT: li a1, 14
|
||||
; VENTUS-NEXT: vmv.v.x v1, a1
|
||||
; VENTUS-NEXT: li a1, 13
|
||||
; VENTUS-NEXT: vblt v0, v1, .LBB0_5
|
||||
; VENTUS-NEXT: # %bb.1: # %if.else
|
||||
; VENTUS-NEXT: vmv.x.s a0, v0
|
||||
; VENTUS-NEXT: li a1, 18
|
||||
; VENTUS-NEXT: bgeu a0, a1, .LBB0_3
|
||||
; VENTUS-NEXT: join v0, v0, .LBB0_2
|
||||
; VENTUS-NEXT: .LBB0_5:
|
||||
; VENTUS-NEXT: join v0, v0, .LBB0_2
|
||||
; VENTUS-NEXT: .LBB0_2: # %cleanup
|
||||
; VENTUS-NEXT: vmv.v.x v0, a1
|
||||
; VENTUS-NEXT: lw ra, -16(sp) # 4-byte Folded Reload
|
||||
; VENTUS-NEXT: addi tp, tp, -16
|
||||
; VENTUS-NEXT: join v0, v0, .LBB0_4
|
||||
; VENTUS-NEXT: .LBB0_3: # %if.end3
|
||||
; VENTUS-NEXT: li a0, 4
|
||||
; VENTUS-NEXT: vmv.v.x v0, a0
|
||||
; VENTUS-NEXT: lw ra, -16(sp) # 4-byte Folded Reload
|
||||
; VENTUS-NEXT: addi tp, tp, -16
|
||||
; VENTUS-NEXT: call _Z13get_global_idj
|
||||
; VENTUS-NEXT: join v0, v0, .LBB0_4
|
||||
; VENTUS-NEXT: .LBB0_4:
|
||||
; VENTUS-NEXT: ret
|
||||
entry:
|
||||
%call = tail call i32 @_Z13get_global_idj(i32 noundef 0)
|
||||
%cmp = icmp slt i32 %call, 14
|
||||
br i1 %cmp, label %cleanup, label %if.else
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%cmp1 = icmp ult i32 %call, 18
|
||||
br i1 %cmp1, label %cleanup, label %if.end3
|
||||
|
||||
if.end3: ; preds = %if.else
|
||||
%call4 = tail call i32 @_Z13get_global_idj(i32 noundef 4)
|
||||
br label %cleanup
|
||||
|
||||
cleanup: ; preds = %if.else, %entry, %if.end3
|
||||
%retval.0 = phi i32 [ %call4, %if.end3 ], [ 13, %entry ], [ 18, %if.else ]
|
||||
ret i32 %retval.0
|
||||
}
|
||||
|
||||
define dso_local spir_kernel void @loop_branch(ptr addrspace(1) nocapture noundef align 4 %A, ptr addrspace(1) nocapture noundef readonly align 4 %B) {
|
||||
; VENTUS-LABEL: loop_branch:
|
||||
; VENTUS: # %bb.0: # %entry
|
||||
; VENTUS-NEXT: addi sp, sp, 16
|
||||
; VENTUS-NEXT: .cfi_def_cfa_offset 16
|
||||
; VENTUS-NEXT: sw ra, -12(sp) # 4-byte Folded Spill
|
||||
; VENTUS-NEXT: sw s0, -16(sp) # 4-byte Folded Spill
|
||||
; VENTUS-NEXT: .cfi_offset ra, 4
|
||||
; VENTUS-NEXT: .cfi_offset s0, 0
|
||||
; VENTUS-NEXT: mv s0, a0
|
||||
; VENTUS-NEXT: vmv.v.x v0, zero
|
||||
; VENTUS-NEXT: call _Z13get_global_idj
|
||||
; VENTUS-NEXT: vmv.x.s a0, v0
|
||||
; VENTUS-NEXT: vmv.v.x v0, zero
|
||||
; VENTUS-NEXT: vmv.v.x v1, a0
|
||||
; VENTUS-NEXT: vbeq v1, v0, .LBB1_4
|
||||
; VENTUS-NEXT: # %bb.1: # %for.body.lr.ph
|
||||
; VENTUS-NEXT: lw a3, 4(s0)
|
||||
; VENTUS-NEXT: lw a1, 0(s0)
|
||||
; VENTUS-NEXT: slli a4, a0, 2
|
||||
; VENTUS-NEXT: add a1, a1, a4
|
||||
; VENTUS-NEXT: lw a2, 0(a1)
|
||||
; VENTUS-NEXT: add a3, a3, a4
|
||||
; VENTUS-NEXT: .LBB1_2: # %for.body
|
||||
; VENTUS-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; VENTUS-NEXT: lw a4, 0(a3)
|
||||
; VENTUS-NEXT: add a2, a2, a4
|
||||
; VENTUS-NEXT: addi a0, a0, -1
|
||||
; VENTUS-NEXT: sw a2, 0(a1)
|
||||
; VENTUS-NEXT: bnez a0, .LBB1_2
|
||||
; VENTUS-NEXT: join v0, v0, .LBB1_3
|
||||
; VENTUS-NEXT: .LBB1_4:
|
||||
; VENTUS-NEXT: join v0, v0, .LBB1_3
|
||||
; VENTUS-NEXT: .LBB1_3: # %for.cond.cleanup
|
||||
; VENTUS-NEXT: lw ra, -12(sp) # 4-byte Folded Reload
|
||||
; VENTUS-NEXT: lw s0, -16(sp) # 4-byte Folded Reload
|
||||
; VENTUS-NEXT: addi sp, sp, -16
|
||||
; VENTUS-NEXT: ret
|
||||
entry:
|
||||
%call = tail call i32 @_Z13get_global_idj(i32 noundef 0)
|
||||
%cmp5.not = icmp eq i32 %call, 0
|
||||
br i1 %cmp5.not, label %for.cond.cleanup, label %for.body.lr.ph
|
||||
|
||||
for.body.lr.ph: ; preds = %entry
|
||||
%arrayidx = getelementptr inbounds i32, ptr addrspace(1) %B, i32 %call
|
||||
%arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %A, i32 %call
|
||||
%.pre = load i32, ptr addrspace(1) %arrayidx1, align 4
|
||||
br label %for.body
|
||||
|
||||
for.cond.cleanup: ; preds = %for.body, %entry
|
||||
ret void
|
||||
|
||||
for.body: ; preds = %for.body.lr.ph, %for.body
|
||||
%0 = phi i32 [ %.pre, %for.body.lr.ph ], [ %add, %for.body ]
|
||||
%i.06 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
|
||||
%1 = load i32, ptr addrspace(1) %arrayidx, align 4
|
||||
%add = add nsw i32 %0, %1
|
||||
store i32 %add, ptr addrspace(1) %arrayidx1, align 4
|
||||
%inc = add nuw nsw i32 %i.06, 1
|
||||
%exitcond.not = icmp eq i32 %inc, %call
|
||||
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
|
||||
}
|
||||
|
||||
define dso_local i32 @branch_in_branch(i32 noundef %dim) local_unnamed_addr {
|
||||
; VENTUS-LABEL: branch_in_branch:
|
||||
; VENTUS: # %bb.0: # %entry
|
||||
; VENTUS-NEXT: addi tp, tp, 16
|
||||
; VENTUS-NEXT: .cfi_def_cfa_offset 16
|
||||
; VENTUS-NEXT: sw ra, -12(sp) # 4-byte Folded Spill
|
||||
; VENTUS-NEXT: sw s0, -16(sp) # 4-byte Folded Spill
|
||||
; VENTUS-NEXT: .cfi_offset ra, 4
|
||||
; VENTUS-NEXT: .cfi_offset s0, 0
|
||||
; VENTUS-NEXT: vmv.v.x v0, zero
|
||||
; VENTUS-NEXT: call _Z13get_global_idj
|
||||
; VENTUS-NEXT: li a0, 14
|
||||
; VENTUS-NEXT: vmv.v.x v1, a0
|
||||
; VENTUS-NEXT: li a0, 13
|
||||
; VENTUS-NEXT: vblt v0, v1, .LBB2_9
|
||||
; VENTUS-NEXT: # %bb.1: # %if.else
|
||||
; VENTUS-NEXT: vmv.x.s s0, v0
|
||||
; VENTUS-NEXT: li a0, 17
|
||||
; VENTUS-NEXT: bltu a0, s0, .LBB2_4
|
||||
; VENTUS-NEXT: # %bb.2: # %if.then2
|
||||
; VENTUS-NEXT: li a0, 1
|
||||
; VENTUS-NEXT: vmv.v.x v0, a0
|
||||
; VENTUS-NEXT: call _Z13get_global_idj
|
||||
; VENTUS-NEXT: vmv.v.x v1, s0
|
||||
; VENTUS-NEXT: vblt v0, v1, .LBB2_5
|
||||
; VENTUS-NEXT: # %bb.3: # %if.then2
|
||||
; VENTUS-NEXT: li a0, 23
|
||||
; VENTUS-NEXT: vmv.v.x v0, a0
|
||||
; VENTUS-NEXT: join v0, v0, .LBB2_6
|
||||
; VENTUS-NEXT: .LBB2_4: # %if.end7
|
||||
; VENTUS-NEXT: li a0, 4
|
||||
; VENTUS-NEXT: vmv.v.x v0, a0
|
||||
; VENTUS-NEXT: lw ra, -12(sp) # 4-byte Folded Reload
|
||||
; VENTUS-NEXT: lw s0, -16(sp) # 4-byte Folded Reload
|
||||
; VENTUS-NEXT: addi tp, tp, -16
|
||||
; VENTUS-NEXT: call _Z13get_global_idj
|
||||
; VENTUS-NEXT: join v0, v0, .LBB2_8
|
||||
; VENTUS-NEXT: .LBB2_5: # %if.then2
|
||||
; VENTUS-NEXT: li a0, 12
|
||||
; VENTUS-NEXT: vmv.v.x v0, a0
|
||||
; VENTUS-NEXT: join v0, v0, .LBB2_6
|
||||
; VENTUS-NEXT: .LBB2_6: # %if.then2
|
||||
; VENTUS-NEXT: vmv.x.s a0, v0
|
||||
; VENTUS-NEXT: join v0, v0, .LBB2_7
|
||||
; VENTUS-NEXT: .LBB2_9:
|
||||
; VENTUS-NEXT: join v0, v0, .LBB2_7
|
||||
; VENTUS-NEXT: .LBB2_7: # %cleanup9
|
||||
; VENTUS-NEXT: vmv.v.x v0, a0
|
||||
; VENTUS-NEXT: lw ra, -12(sp) # 4-byte Folded Reload
|
||||
; VENTUS-NEXT: lw s0, -16(sp) # 4-byte Folded Reload
|
||||
; VENTUS-NEXT: addi tp, tp, -16
|
||||
; VENTUS-NEXT: join v0, v0, .LBB2_8
|
||||
; VENTUS-NEXT: .LBB2_8:
|
||||
; VENTUS-NEXT: ret
|
||||
entry:
|
||||
%call = tail call i32 @_Z13get_global_idj(i32 noundef 0)
|
||||
%cmp = icmp slt i32 %call, 14
|
||||
br i1 %cmp, label %cleanup9, label %if.else
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%cmp1 = icmp ult i32 %call, 18
|
||||
br i1 %cmp1, label %if.then2, label %if.end7
|
||||
|
||||
if.then2: ; preds = %if.else
|
||||
%call3 = tail call i32 @_Z13get_global_idj(i32 noundef 1)
|
||||
%cmp4 = icmp sgt i32 %call, %call3
|
||||
%. = select i1 %cmp4, i32 12, i32 23
|
||||
br label %cleanup9
|
||||
|
||||
if.end7: ; preds = %if.else
|
||||
%call8 = tail call i32 @_Z13get_global_idj(i32 noundef 4)
|
||||
br label %cleanup9
|
||||
|
||||
cleanup9: ; preds = %entry, %if.end7, %if.then2
|
||||
%retval.1 = phi i32 [ %., %if.then2 ], [ %call8, %if.end7 ], [ 13, %entry ]
|
||||
ret i32 %retval.1
|
||||
}
|
||||
|
||||
; Function Attrs: convergent nofree norecurse nounwind memory(argmem: readwrite) vscale_range(1,2048)
|
||||
define dso_local spir_kernel void @double_loop(ptr addrspace(1) nocapture noundef align 4 %A, ptr addrspace(1) nocapture noundef readonly align 4 %B) {
|
||||
; VENTUS-LABEL: double_loop:
|
||||
; VENTUS: # %bb.0: # %entry
|
||||
; VENTUS-NEXT: addi sp, sp, 16
|
||||
; VENTUS-NEXT: .cfi_def_cfa_offset 16
|
||||
; VENTUS-NEXT: sw ra, -12(sp) # 4-byte Folded Spill
|
||||
; VENTUS-NEXT: sw s0, -16(sp) # 4-byte Folded Spill
|
||||
; VENTUS-NEXT: .cfi_offset ra, 4
|
||||
; VENTUS-NEXT: .cfi_offset s0, 0
|
||||
; VENTUS-NEXT: mv s0, a0
|
||||
; VENTUS-NEXT: vmv.v.x v0, zero
|
||||
; VENTUS-NEXT: call _Z13get_global_idj
|
||||
; VENTUS-NEXT: vmv.x.s a0, v0
|
||||
; VENTUS-NEXT: vmv.v.x v0, zero
|
||||
; VENTUS-NEXT: vmv.v.x v1, a0
|
||||
; VENTUS-NEXT: vbeq v1, v0, .LBB3_6
|
||||
; VENTUS-NEXT: # %bb.1: # %for.cond1.preheader.lr.ph
|
||||
; VENTUS-NEXT: li a1, 0
|
||||
; VENTUS-NEXT: lw a4, 4(s0)
|
||||
; VENTUS-NEXT: lw a2, 0(s0)
|
||||
; VENTUS-NEXT: slli a5, a0, 2
|
||||
; VENTUS-NEXT: add a2, a2, a5
|
||||
; VENTUS-NEXT: lw a3, 0(a2)
|
||||
; VENTUS-NEXT: add a4, a4, a5
|
||||
; VENTUS-NEXT: .LBB3_2: # %for.cond1.preheader
|
||||
; VENTUS-NEXT: # =>This Loop Header: Depth=1
|
||||
; VENTUS-NEXT: # Child Loop BB3_3 Depth 2
|
||||
; VENTUS-NEXT: mv a5, a0
|
||||
; VENTUS-NEXT: .LBB3_3: # %for.body4
|
||||
; VENTUS-NEXT: # Parent Loop BB3_2 Depth=1
|
||||
; VENTUS-NEXT: # => This Inner Loop Header: Depth=2
|
||||
; VENTUS-NEXT: lw a6, 0(a4)
|
||||
; VENTUS-NEXT: add a3, a3, a6
|
||||
; VENTUS-NEXT: addi a5, a5, -1
|
||||
; VENTUS-NEXT: sw a3, 0(a2)
|
||||
; VENTUS-NEXT: bnez a5, .LBB3_3
|
||||
; VENTUS-NEXT: # %bb.4: # %for.cond1.for.cond.cleanup3_crit_edge
|
||||
; VENTUS-NEXT: # in Loop: Header=BB3_2 Depth=1
|
||||
; VENTUS-NEXT: addi a1, a1, 1
|
||||
; VENTUS-NEXT: bne a1, a0, .LBB3_2
|
||||
; VENTUS-NEXT: join v0, v0, .LBB3_5
|
||||
; VENTUS-NEXT: .LBB3_6:
|
||||
; VENTUS-NEXT: join v0, v0, .LBB3_5
|
||||
; VENTUS-NEXT: .LBB3_5: # %for.cond.cleanup
|
||||
; VENTUS-NEXT: lw ra, -12(sp) # 4-byte Folded Reload
|
||||
; VENTUS-NEXT: lw s0, -16(sp) # 4-byte Folded Reload
|
||||
; VENTUS-NEXT: addi sp, sp, -16
|
||||
; VENTUS-NEXT: ret
|
||||
entry:
|
||||
%call = tail call i32 @_Z13get_global_idj(i32 noundef 0)
|
||||
%cmp16.not = icmp eq i32 %call, 0
|
||||
br i1 %cmp16.not, label %for.cond.cleanup, label %for.cond1.preheader.lr.ph
|
||||
|
||||
for.cond1.preheader.lr.ph: ; preds = %entry
|
||||
%arrayidx = getelementptr inbounds i32, ptr addrspace(1) %B, i32 %call
|
||||
%arrayidx5 = getelementptr inbounds i32, ptr addrspace(1) %A, i32 %call
|
||||
%.pre.pre = load i32, ptr addrspace(1) %arrayidx5, align 4
|
||||
br label %for.cond1.preheader
|
||||
|
||||
for.cond1.preheader: ; preds = %for.cond1.preheader.lr.ph, %for.cond1.for.cond.cleanup3_crit_edge
|
||||
%.pre = phi i32 [ %.pre.pre, %for.cond1.preheader.lr.ph ], [ %add, %for.cond1.for.cond.cleanup3_crit_edge ]
|
||||
%i.017 = phi i32 [ 0, %for.cond1.preheader.lr.ph ], [ %inc7, %for.cond1.for.cond.cleanup3_crit_edge ]
|
||||
br label %for.body4
|
||||
|
||||
for.cond.cleanup: ; preds = %for.cond1.for.cond.cleanup3_crit_edge, %entry
|
||||
ret void
|
||||
|
||||
for.cond1.for.cond.cleanup3_crit_edge: ; preds = %for.body4
|
||||
%inc7 = add nuw nsw i32 %i.017, 1
|
||||
%exitcond18.not = icmp eq i32 %inc7, %call
|
||||
br i1 %exitcond18.not, label %for.cond.cleanup, label %for.cond1.preheader
|
||||
|
||||
for.body4: ; preds = %for.cond1.preheader, %for.body4
|
||||
%0 = phi i32 [ %.pre, %for.cond1.preheader ], [ %add, %for.body4 ]
|
||||
%j.015 = phi i32 [ 0, %for.cond1.preheader ], [ %inc, %for.body4 ]
|
||||
%1 = load i32, ptr addrspace(1) %arrayidx, align 4
|
||||
%add = add nsw i32 %0, %1
|
||||
store i32 %add, ptr addrspace(1) %arrayidx5, align 4
|
||||
%inc = add nuw nsw i32 %j.015, 1
|
||||
%exitcond.not = icmp eq i32 %inc, %call
|
||||
br i1 %exitcond.not, label %for.cond1.for.cond.cleanup3_crit_edge, label %for.body4
|
||||
}
|
||||
|
||||
; Function Attrs: convergent nofree norecurse nounwind memory(argmem: readwrite) vscale_range(1,2048)
|
||||
define dso_local spir_kernel void @loop_switch(ptr addrspace(1) nocapture noundef align 4 %A, ptr addrspace(1) nocapture noundef readonly align 4 %B) {
|
||||
; VENTUS-LABEL: loop_switch:
|
||||
; VENTUS: # %bb.0: # %entry
|
||||
; VENTUS-NEXT: addi sp, sp, 16
|
||||
; VENTUS-NEXT: .cfi_def_cfa_offset 16
|
||||
; VENTUS-NEXT: sw ra, -12(sp) # 4-byte Folded Spill
|
||||
; VENTUS-NEXT: sw s0, -16(sp) # 4-byte Folded Spill
|
||||
; VENTUS-NEXT: .cfi_offset ra, 4
|
||||
; VENTUS-NEXT: .cfi_offset s0, 0
|
||||
; VENTUS-NEXT: mv s0, a0
|
||||
; VENTUS-NEXT: vmv.v.x v0, zero
|
||||
; VENTUS-NEXT: call _Z13get_global_idj
|
||||
; VENTUS-NEXT: vmv.x.s a0, v0
|
||||
; VENTUS-NEXT: vmv.v.x v0, zero
|
||||
; VENTUS-NEXT: vmv.v.x v1, a0
|
||||
; VENTUS-NEXT: vbeq v1, v0, .LBB4_10
|
||||
; VENTUS-NEXT: # %bb.1: # %for.body.lr.ph
|
||||
; VENTUS-NEXT: li a1, 0
|
||||
; VENTUS-NEXT: lw a2, 4(s0)
|
||||
; VENTUS-NEXT: lw a5, 0(s0)
|
||||
; VENTUS-NEXT: slli a3, a0, 2
|
||||
; VENTUS-NEXT: add a2, a2, a3
|
||||
; VENTUS-NEXT: add a3, a5, a3
|
||||
; VENTUS-NEXT: addi a4, a5, 8
|
||||
; VENTUS-NEXT: addi a5, a5, 4
|
||||
; VENTUS-NEXT: li a6, 1
|
||||
; VENTUS-NEXT: li a7, 2
|
||||
; VENTUS-NEXT: j .LBB4_5
|
||||
; VENTUS-NEXT: .LBB4_2: # %sw.default
|
||||
; VENTUS-NEXT: # in Loop: Header=BB4_5 Depth=1
|
||||
; VENTUS-NEXT: lw t1, 0(a2)
|
||||
; VENTUS-NEXT: mv t0, a3
|
||||
; VENTUS-NEXT: .LBB4_3: # %for.inc.sink.split
|
||||
; VENTUS-NEXT: # in Loop: Header=BB4_5 Depth=1
|
||||
; VENTUS-NEXT: lw t2, 0(t0)
|
||||
; VENTUS-NEXT: add t1, t2, t1
|
||||
; VENTUS-NEXT: sw t1, 0(t0)
|
||||
; VENTUS-NEXT: .LBB4_4: # %for.inc
|
||||
; VENTUS-NEXT: # in Loop: Header=BB4_5 Depth=1
|
||||
; VENTUS-NEXT: addi a1, a1, 1
|
||||
; VENTUS-NEXT: beq a0, a1, .LBB4_9
|
||||
; VENTUS-NEXT: join v0, v0, .LBB4_9
|
||||
; VENTUS-NEXT: .LBB4_5: # %for.body
|
||||
; VENTUS-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; VENTUS-NEXT: beqz a1, .LBB4_4
|
||||
; VENTUS-NEXT: # %bb.6: # %for.body
|
||||
; VENTUS-NEXT: # in Loop: Header=BB4_5 Depth=1
|
||||
; VENTUS-NEXT: mv t0, a5
|
||||
; VENTUS-NEXT: li t1, 2
|
||||
; VENTUS-NEXT: beq a1, a6, .LBB4_3
|
||||
; VENTUS-NEXT: # %bb.7: # %for.body
|
||||
; VENTUS-NEXT: # in Loop: Header=BB4_5 Depth=1
|
||||
; VENTUS-NEXT: bne a1, a7, .LBB4_2
|
||||
; VENTUS-NEXT: # %bb.8: # %sw.bb4
|
||||
; VENTUS-NEXT: # in Loop: Header=BB4_5 Depth=1
|
||||
; VENTUS-NEXT: li t1, 23
|
||||
; VENTUS-NEXT: mv t0, a4
|
||||
; VENTUS-NEXT: j .LBB4_3
|
||||
; VENTUS-NEXT: .LBB4_10:
|
||||
; VENTUS-NEXT: join v0, v0, .LBB4_9
|
||||
; VENTUS-NEXT: .LBB4_9: # %for.cond.cleanup
|
||||
; VENTUS-NEXT: lw ra, -12(sp) # 4-byte Folded Reload
|
||||
; VENTUS-NEXT: lw s0, -16(sp) # 4-byte Folded Reload
|
||||
; VENTUS-NEXT: addi sp, sp, -16
|
||||
; VENTUS-NEXT: ret
|
||||
entry:
|
||||
%call = tail call i32 @_Z13get_global_idj(i32 noundef 0)
|
||||
%cmp21.not = icmp eq i32 %call, 0
|
||||
br i1 %cmp21.not, label %for.cond.cleanup, label %for.body.lr.ph
|
||||
|
||||
for.body.lr.ph: ; preds = %entry
|
||||
%arrayidx7 = getelementptr inbounds i32, ptr addrspace(1) %B, i32 %call
|
||||
%arrayidx8 = getelementptr inbounds i32, ptr addrspace(1) %A, i32 %call
|
||||
%arrayidx5 = getelementptr inbounds i32, ptr addrspace(1) %A, i32 2
|
||||
%arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %A, i32 1
|
||||
br label %for.body
|
||||
|
||||
for.cond.cleanup: ; preds = %for.inc, %entry
|
||||
ret void
|
||||
|
||||
for.body: ; preds = %for.body.lr.ph, %for.inc
|
||||
%i.022 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.inc ]
|
||||
switch i32 %i.022, label %sw.default [
|
||||
i32 0, label %for.inc
|
||||
i32 1, label %for.inc.sink.split
|
||||
i32 2, label %sw.bb4
|
||||
]
|
||||
|
||||
sw.bb4: ; preds = %for.body
|
||||
br label %for.inc.sink.split
|
||||
|
||||
sw.default: ; preds = %for.body
|
||||
%0 = load i32, ptr addrspace(1) %arrayidx7, align 4
|
||||
br label %for.inc.sink.split
|
||||
|
||||
for.inc.sink.split: ; preds = %for.body, %sw.default, %sw.bb4
|
||||
%arrayidx2.sink24 = phi ptr addrspace(1) [ %arrayidx5, %sw.bb4 ], [ %arrayidx8, %sw.default ], [ %arrayidx2, %for.body ]
|
||||
%.sink23 = phi i32 [ 23, %sw.bb4 ], [ %0, %sw.default ], [ 2, %for.body ]
|
||||
%1 = load i32, ptr addrspace(1) %arrayidx2.sink24, align 4
|
||||
%add3 = add nsw i32 %1, %.sink23
|
||||
store i32 %add3, ptr addrspace(1) %arrayidx2.sink24, align 4
|
||||
br label %for.inc
|
||||
|
||||
for.inc: ; preds = %for.inc.sink.split, %for.body
|
||||
%inc = add nuw nsw i32 %i.022, 1
|
||||
%exitcond.not = icmp eq i32 %inc, %call
|
||||
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
|
||||
}
|
||||
|
||||
; Function Attrs: convergent mustprogress nofree nounwind willreturn memory(none)
|
||||
declare dso_local i32 @_Z13get_global_idj(i32 noundef) local_unnamed_addr
|
||||
|
||||
Loading…
Reference in New Issue