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Fix VI instruction codegen bug && disable declare-opencl-builtins option for opencl

This commit is contained in:
zhoujingya 2023-03-20 16:30:08 +08:00
parent 93a71a718b
commit dfc6b4d7f0
3 changed files with 39 additions and 39 deletions
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3
clang/lib/Driver/ToolChains/Clang.cpp
View File

@ -3439,7 +3439,8 @@ static void RenderOpenCLOptions(const ArgList &Args, ArgStringList &CmdArgs,
(Args.hasArg(options::OPT_cl_std_EQ) && types::isSrcFile(InputType))) &&
!Args.hasArg(options::OPT_cl_no_stdinc)) {
CmdArgs.push_back("-finclude-default-header");
CmdArgs.push_back("-fdeclare-opencl-builtins");
// WORKAROUND: still don't know whether this option has other impacts
// CmdArgs.push_back("-fdeclare-opencl-builtins");
}
}

35
llvm/lib/Target/RISCV/VentusInstrInfo.td
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@ -374,6 +374,41 @@ def simm11 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<11>(Imm);}]> {
let OperandType = "OPERAND_SIMM11";
let OperandNamespace = "RISCVOp";
}
def simm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
let ParserMatchClass = SImmAsmOperand<5>;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeSImmOperand<5>";
let OperandType = "OPERAND_SIMM5";
let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (MCOp.evaluateAsConstantImm(Imm))
return isInt<5>(Imm);
return MCOp.isBareSymbolRef();
}];
}
def SImm5Plus1AsmOperand : AsmOperandClass {
let Name = "SImm5Plus1";
let RenderMethod = "addImmOperands";
let DiagnosticType = "InvalidSImm5Plus1";
}
def simm5_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT,
[{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
let ParserMatchClass = SImm5Plus1AsmOperand;
let OperandType = "OPERAND_SIMM5_PLUS1";
let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (MCOp.evaluateAsConstantImm(Imm))
return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
return MCOp.isBareSymbolRef();
}];
}
def simm5_plus1_nonzero : ImmLeaf<XLenVT,
[{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>;
def simm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<12>(Imm);}]> {
let ParserMatchClass = SImmAsmOperand<12>;

40
llvm/lib/Target/RISCV/VentusInstrInfoV.td
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@ -28,8 +28,8 @@ multiclass PatVXIBin<SDPatternOperator Op, list<RVInst> Insts> {
(XLenVT (Insts[1] VGPR:$rs1, GPR:$rs2))>;
if !eq(!size(Insts), 3) then
def : Pat<(XLenVT (Op (XLenVT VGPR:$rs1), uimm5:$imm)),
(XLenVT (Insts[2] VGPR:$rs1, uimm5:$imm))>;
def : Pat<(XLenVT (Op (XLenVT VGPR:$rs1), simm5:$imm)),
(XLenVT (Insts[2] VGPR:$rs1, simm5:$imm))>;
}
// RVV VV, VF, FV instruction pattern class for floating point binary operations
multiclass PatVFRBin<SDPatternOperator Op, list<RVInst> Insts> {
@ -151,42 +151,6 @@ class VTypeIOp<int VTypeINum> : Operand<XLenVT> {
def VTypeIOp10 : VTypeIOp<10>;
def VTypeIOp11 : VTypeIOp<11>;
def simm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
let ParserMatchClass = SImmAsmOperand<5>;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeSImmOperand<5>";
let OperandType = "OPERAND_SIMM5";
let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (MCOp.evaluateAsConstantImm(Imm))
return isInt<5>(Imm);
return MCOp.isBareSymbolRef();
}];
}
def SImm5Plus1AsmOperand : AsmOperandClass {
let Name = "SImm5Plus1";
let RenderMethod = "addImmOperands";
let DiagnosticType = "InvalidSImm5Plus1";
}
def simm5_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT,
[{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
let ParserMatchClass = SImm5Plus1AsmOperand;
let OperandType = "OPERAND_SIMM5_PLUS1";
let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (MCOp.evaluateAsConstantImm(Imm))
return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
return MCOp.isBareSymbolRef();
}];
}
def simm5_plus1_nonzero : ImmLeaf<XLenVT,
[{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>;
//===----------------------------------------------------------------------===//
// Scheduling definitions.
//===----------------------------------------------------------------------===//