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Add definition for vfexp/vftta

This commit is contained in:
zhoujing 2023-01-20 09:57:19 +08:00
parent 0fc446fd81
commit 93143b5b35
1 changed files with 17 additions and 2 deletions
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19
llvm/lib/Target/RISCV/VentusInstrInfo.td
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@ -928,11 +928,26 @@ def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">,
//===----------------------------------------------------------------------===//
// imm12 is divided into 4 x 3bits to encode extended register range.
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
def REGEXT : RVInstI<0b010, OPC_CUSTOM_0, (outs GPR:$rd),
(ins GPR:$rs1, simm12:$imm12),
"regext", "$rd, $rs1, $imm12">;
def VFEXP : RVInstI<0b010, OPC_CUSTOM_0, (outs VGPR:$rd),
(ins VGPR:$vs2),"vfexp", "$rd, $vs2"> {
bits<5> vs2;
let rs1 = 0;
let Inst{24-20} = vs2;
let Inst{31-25} = 0b0000101;
}
let Constraints = "$rd_wb = $rd" in
def VFTTA : RVInstI<0b000, OPC_CUSTOM_0, (outs VGPR:$rd_wb),
(ins VGPR:$rd, VGPR:$vs2, VGPR:$rs1),
"vftta.vv", "$rd, $vs2, $rs1"> {
bits<5> vs2;
let Inst{24-20} = vs2;
let Inst{31-25} = 0b0000011;
}
}
//===----------------------------------------------------------------------===//
// Privileged instructions
//===----------------------------------------------------------------------===//