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[VENTUS][RISCV] Fix private memory load/store instructions definitions.

This commit is contained in:
yanming 2023-07-07 11:12:24 +08:00
parent be2463898a
commit f5df45650f
2 changed files with 13 additions and 33 deletions
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23
llvm/lib/Target/RISCV/VentusInstrFormatsV.td
View File

@ -62,29 +62,6 @@ class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
let Opcode = OPC_OP_V.Value;
}
// vsetvli inst format is used by private memory loads VLW/VLH/VLB
class RVInstSetVLVLi<dag outs, dag ins, string opcodestr, string argstr>
: RVInstSetVLi<outs, ins, opcodestr, argstr> {
bits<5> vd;
bits<11> imm11;
let Inst{31} = 1;
let Inst{30-20} = imm11;
let Inst{11-7} = vd;
}
// vsetvli inst format is used by private memory stores VSW/VSH/VSB
class RVInstSetVSVLi<dag outs, dag ins, string opcodestr, string argstr>
: RVInstSetVLi<outs, ins, opcodestr, argstr> {
bits<5> vd;
bits<11> imm11;
let Inst{31} = 0;
let Inst{30-25} = imm11{10-5};
let Inst{24-20} = vd;
let Inst{11-7} = imm11{4-0};
}
class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {

23
llvm/lib/Target/RISCV/VentusInstrInfoV.td
View File

@ -683,17 +683,20 @@ class Branch_i<bits<3> funct3, string opcodestr>
}
// Private memory load/store instructions
class VENTUS_VL<bits<3> funct3, string opcodestr>:
RVInstSetVLVLi<(outs VGPR:$vd), (ins VGPRMem:$vs1, simm11:$imm11),
opcodestr # ".v", "$vd, ${imm11}(${vs1})"> {
let Inst{14-12} = funct3;
let Opcode = OPC_CUSTOM_1.Value;
class VENTUS_VL<bits<3> funct3, string opcodestr>
: RVInstI<funct3, OPC_OP_V, (outs VGPR:$rd),
(ins VGPRMem:$rs1, simm11:$imm12),
opcodestr # ".v", "$rd, ${imm12}(${rs1})"> {
let Inst{31} = 0;
let Inst{30-20} = imm12{10-0};
}
class VENTUS_VS<bits<3> funct3, string opcodestr>:
RVInstSetVSVLi<(outs), (ins VGPR:$vd, VGPRMem:$vs1, simm11:$imm11),
opcodestr # ".v", "$vd, ${imm11}(${vs1})"> {
let Inst{14-12} = funct3;
let Opcode = OPC_CUSTOM_1.Value;
class VENTUS_VS<bits<3> funct3, string opcodestr>
: RVInstS<funct3, OPC_OP_V, (outs),
(ins VGPR:$rs2, VGPRMem:$rs1, simm11:$imm12),
opcodestr # ".v", "$rs2, ${imm12}(${rs1})"> {
let Inst{31} = 1;
let Inst{30-25} = imm12{10-5};
let Inst{11-7} = imm12{4-0};
}
// Local/Global memory load/store instructions