OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 2
Code Issues Packages Projects Releases Wiki Activity
444,602 Commits 29 Branches 0 Tags 2.2 GiB
Commit Graph

444602 Commits

Author SHA1 Message Date
zhoujing 9da5d1dbb1 [VENTUS][RISCV][NFC] Disable macro-redefined warining 2023-07-27 09:31:37 +08:00
zhoujing 0780087477 [VENTUS][RISCV][fix] Fix the register usage calculation of VGPR/GPR 2023-07-26 17:31:13 +08:00
zhoujing 6f502d2c33 [VENTUS][RISCV][fix] Set correct datalayout for different language options 2023-07-25 16:55:05 +08:00
zhoujing 85cf676b2c [VENTUS][RISCV][feat] Accelerate libclc building process 
Disable builtin cmake script defined in libclc by upstream to accelerate ventus
libclc building process
 2023-07-25 10:54:40 +08:00
zhoujing 9d56abe113 [VENTUS][RISCV][NFC] Add comment && Typo fix 2023-07-25 10:33:34 +08:00
zhoujing 1df9e6cdae [VENTUS][RISCV][feat] Initialize adding ventus resource usage information to ELF file 2023-07-25 10:22:33 +08:00
zhoujing dbdb0cbdfa [VENTUS][RISCV][feat] Add API to calculate VGPR/SGPR register usage information 2023-07-24 17:27:42 +08:00
zhoujing 1df9b6223c [VENTUS][RISCV][feat] Add atomic instructions VGPR index support 2023-07-24 13:38:42 +08:00
zhoujing 4a74fa2d0c [VENTUS][RISCV][feat] Add findUnusedRegister function in RISCVRegisterInfo 2023-07-24 13:02:26 +08:00
zhoujing 381564b4fd [VENTUS][RISCV][fix] Only convert .text section and ignore all other sections 2023-07-24 09:50:27 +08:00
zhoujing 623ca8b4ba [VENTUS][RISCV][fix] Fix stack size calculation bug 2023-07-21 18:02:33 +08:00
zhoujing 2069ca56d3 [VENTUS][RISCV][fix] Fix bug which cause '*' symbol in vmem file 
hexdump tool will substract continous same bit code into '*' for simplicity and
space save, but this will cause bugs in pocl
 2023-07-21 11:20:00 +08:00
zhoujing bdf01afb7d [VENTUS][RISCV][fix] Add CSR_WGID definition 2023-07-21 10:01:38 +08:00
zhoujing 258d76a7c8 [VENTUS][RISCV][fix] Fix get_global_id_z function bug 2023-07-19 19:32:26 +08:00
zhoujing 1a6ead3f43 [VENTUS][RISCV][fix] Fix workitem function implementation 2023-07-19 17:45:35 +08:00
zhoujing b8223e72bd [VENTUS][RISCV][feat] Building libclc library into object file other than archive file 
In our previous design, the libclc library is built into static library which make the generated
ELF file having a large size, now we change compiler and linker option to make generated ELF file size much smaller, detail information can be seen in this pull request https://github.com/THU-DSP-LAB/pocl/pull/11
 2023-07-17 21:39:02 +08:00
zhoujing cb6fe8a2a1 [VENTUS][RISCV][fix] Setting PATH in assemble.sh to get correct tools 2023-07-14 11:58:45 +08:00
zhoujing fabfe7b62c [VENTUS][RISCV][test] Update MC test case 2023-07-14 10:24:18 +08:00
zhoujing 2b2f2342e1 [VENTUS][RISCV][NFC] Clean codes 2023-07-14 09:13:15 +08:00
zhoujing f026e3e0aa [VENTUS][RISCV][fix] Fix spike_end wrong section bug 2023-07-13 21:27:55 +08:00
zhoujing 3719c07dc0 [VENTUS][RISCV][fix] Modify JOIN instruction to use X0 rather than V0 2023-07-13 17:01:36 +08:00
zhoujingya a5c1106e25 [VENTUS][RISCV][fix] Remove redundant codes 2023-07-13 13:53:59 +08:00
zhoujing a9d1e6f524 [VENTUS][RISCV][fix] Avoid MBB label lost after optimization 2023-07-13 13:26:13 +08:00
zhoujing 209306abc9 [VENTUS][RISCV][libclc] Add more soft float function support 2023-07-13 13:24:03 +08:00
zhoujing d2c3e47f6a [VENTUS][RISCV][fix] Remove redundant fma funtion 2023-07-13 09:49:30 +08:00
zhoujing 760e86baf2 [VENTUS][RISCV][fix&feat] Add cl_khr_fp64 support and add missing header file 2023-07-13 09:21:50 +08:00
zhoujing 7b949c1868 [VENTUS][RISCV][libclc] Add additional soft float support functions 2023-07-12 21:02:52 +08:00
zhoujing a5b2d952d7 [VENTUS][RISCV][libclc] Add soft float support 2023-07-12 16:40:11 +08:00
zhoujing e6ae0f7ac6 [VENTUS][RISCV][fix] Disable simple loop optimization to call llvm memset/memcpy intrinsics 2023-07-11 16:26:49 +08:00
Jules-Kong 5215f4da1e [VENTUS][RISCV] Add option --mattr=+v 
The option --mattr=+v was lost before, causing the ventus compiler to generate
some unknown instructions.
 2023-07-11 14:04:00 +08:00
zhoujing 77c0b15cff [VENTUS][RISCV][test&fix] Add more MC test and fix related bugs 2023-07-11 11:17:55 +08:00
zhoujing e7b96af8fa [VENTUS][RISCV][test] Add MC test for ventus customized instructions 2023-07-10 16:27:50 +08:00
zhoujing b2d9d1f535 [VENTUS][RISCV][fix] Disable all widening vector arithmetic instructions codegen 2023-07-10 10:47:53 +08:00
zhoujing 1bfef21c65 [VENTUS][RISCV][fix] Moving 'tohost' and 'fromhost' from section 'tohost' to '.data' 
We change this because we find function jump bugs in rodinia GPU test
 2023-07-10 09:12:02 +08:00
yanming 4c099fb3d5 [VENTUS][RISCV] Move `regext insertion pass` after `insert join instruction pass`. 2023-07-07 17:22:27 +08:00
yanming d37e92610d [VENTUS][RISCV] Remove redundant code and enable regext insertion pass when verify machineinstrs. 2023-07-07 17:08:42 +08:00
zhoujing 9899aee134 [VENTUS][RISCV][fix] Fix undefined symbol errors in libclc 
We expand all the macros used in these changed files hand by hand, a little stupid, but it works
 2023-07-07 16:24:29 +08:00
zhoujing 7da8486eb3 [VENTUS][RISCV][feat] Add data structure interface for collecting ventus program information 2023-07-07 15:42:25 +08:00
zhoujing 4fea917aec [VENTUS][RISCV][fix] Fix pattern match errors 2023-07-07 13:48:55 +08:00
yanming c0b7829a87 [VENTUS][RISCV] Skip TargetOpcode::KILL instruction in regext insertion pass. 2023-07-07 13:46:12 +08:00
yanming bd1c51d245 [TableGen] Set tied to operand custom flag if current operand has tied operand. 2023-07-07 12:38:53 +08:00
yanming f5df45650f [VENTUS][RISCV] Fix private memory load/store instructions definitions. 2023-07-07 11:12:24 +08:00
zhoujing be2463898a [VENTUS][RISCV][Fix] Remove 64bits related codes in gen_convert.py 2023-07-07 09:59:44 +08:00
zhoujing 21e0b87130 [VENTUS][RISCV][Fix] Typo fix 2023-07-07 09:42:55 +08:00
zhoujing 24c8b19c42 [VENTUS][RISCV][Fix] Remove 64bits related codes in gen_convert.py 
This file will finally generate convert.cl file
 2023-07-07 09:40:34 +08:00
zhoujing fb8b0daa4d [VENTUS][RISCV][fix] Fix building errors caused by lost semicolon in libclc 2023-07-07 09:35:22 +08:00
zhoujing ec10e99633 Revert "[VENTUS][RISCV][fix] fix undefined symbol erros in libclc library" 
This reverts commit e8492c3117.
 2023-07-07 09:32:44 +08:00
zhoujing 589c4c2c81 [VENTUS][RISCV][NFC] Remove unused codes 2023-07-06 23:44:30 +08:00
zhoujing 21287dec72 [VENTUS][RISCV][fix] Fix undefined symbols in lgamma_r.cl file 2023-07-06 22:20:42 +08:00
zhoujing e8492c3117 [VENTUS][RISCV][fix] fix undefined symbol erros in libclc library 2023-07-06 21:48:53 +08:00