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[VENTUS][RISCV][test] Add MC test for ventus customized instructions

This commit is contained in:
zhoujing 2023-07-10 16:27:50 +08:00
parent b2d9d1f535
commit e7b96af8fa
3 changed files with 77 additions and 2 deletions
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4
llvm/lib/Target/RISCV/VentusInstrInfoV.td
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@ -690,14 +690,14 @@ class Branch_i<bits<3> funct3, string opcodestr>
// Private memory load/store instructions
class VENTUS_VL<bits<3> funct3, string opcodestr>
: RVInstI<funct3, OPC_OP_V, (outs VGPR:$rd),
: RVInstI<funct3, OPC_CUSTOM_1, (outs VGPR:$rd),
(ins VGPRMem:$rs1, simm11:$imm12),
opcodestr # ".v", "$rd, ${imm12}(${rs1})"> {
let Inst{31} = 0;
let Inst{30-20} = imm12{10-0};
}
class VENTUS_VS<bits<3> funct3, string opcodestr>
: RVInstS<funct3, OPC_OP_V, (outs),
: RVInstS<funct3, OPC_CUSTOM_1, (outs),
(ins VGPR:$rs2, VGPRMem:$rs1, simm11:$imm12),
opcodestr # ".v", "$rs2, ${imm12}(${rs1})"> {
let Inst{31} = 1;

46
llvm/test/MC/RISCV/ventus/vload.s Normal file
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@ -0,0 +1,46 @@
# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v %s \
# RUN: | llvm-objdump -d --mattr=+v - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
vlw12.v v6, 4(v1)
# CHECK-INST: vlw12.v v6, 4(v1)
# CHECK-ENCODING: [0x7b,0xa3,0x40,0x00]
vlh12.v v6, 4(v1)
# CHECK-INST: vlh12.v v6, 4(v1)
# CHECK-ENCODING: [0x7b,0x93,0x40,0x00]
vlb12.v v6, 4(v1)
# CHECK-INST: vlb12.v v6, 4(v1)
# CHECK-ENCODING: [0x7b,0x83,0x40,0x00]
vlhu12.v v6, 8(v1)
# CHECK-INST: vlhu12.v v6, 8(v1)
# CHECK-ENCODING: [0x7b,0xd3,0x80,0x00]
vlbu12.v v6, 12(v1)
# CHECK-INST: vlbu12.v v6, 12(v1)
# CHECK-ENCODING: [0x7b,0xc3,0xc0,0x00]
vlw.v v6, 12(v1)
# CHECK-INST: vlw.v v6, 12(v1)
# CHECK-ENCODING: [0x2b,0xa3,0xc0,0x00]
vlh.v v6, 12(v1)
# CHECK-INST: vlh.v v6, 12(v1)
# CHECK-ENCODING: [0x2b,0x93,0xc0,0x00]
vlb.v v6, 12(v1)
# CHECK-INST: vlb.v v6, 12(v1)
# CHECK-ENCODING: [0x2b,0x83,0xc0,0x00]
vlhu.v v6, 12(v1)
# CHECK-INST: vlhu.v v6, 12(v1)
# CHECK-ENCODING: [0x2b,0xd3,0xc0,0x00]
vlbu.v v6, 12(v1)
# CHECK-INST: vlbu.v v6, 12(v1)
# CHECK-ENCODING: [0x2b,0xc3,0xc0,0x00]

29
llvm/test/MC/RISCV/ventus/vstore.s Normal file
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@ -0,0 +1,29 @@
# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v %s \
# RUN: | llvm-objdump -d --mattr=+v - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
vsw12.v v6, 4(v1)
# CHECK-INST: vsw12.v v6, 4(v1)
# CHECK-ENCODING: [0x7b,0xe2,0x60,0x00]
vsh12.v v6, 4(v1)
# CHECK-INST: vsh12.v v6, 4(v1)
# CHECK-ENCODING: [0x7b,0xb2,0x60,0x00]
vsb12.v v6, 4(v1)
# CHECK-INST: vsb12.v v6, 4(v1)
# CHECK-ENCODING: [0x7b,0xf2,0x60,0x00]
vsw.v v6, 4(v1)
# CHECK-INST: vsw.v v6, 4(v1)
# CHECK-ENCODING: [0x2b,0xa2,0x60,0x80]
vsh.v v6, 4(v1)
# CHECK-INST: vsh.v v6, 4(v1)
# CHECK-ENCODING: [0x2b,0x92,0x60,0x80]
vsb.v v6, 4(v1)
# CHECK-INST: vsb.v v6, 4(v1)
# CHECK-ENCODING: [0x2b,0x82,0x60,0x80]