[VENTUS][RISCV] Move `regext insertion pass` after `insert join instruction pass`.
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@ -271,12 +271,12 @@ bool RISCVPassConfig::addGlobalInstructionSelect() {
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void RISCVPassConfig::addPreSched2() {}
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void RISCVPassConfig::addPreEmitPass() {
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addPass(createVentusInsertJoinToVBranchPass());
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// NOTE: This pass must be at the end of all optimization passes, as it
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// breaks the def-use chain!
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// Insert regext instruction for instruction whose register id is greater
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// than 31.
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addPass(createVentusRegextInsertionPass());
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addPass(createVentusInsertJoinToVBranchPass());
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addPass(&BranchRelaxationPassID);
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addPass(createRISCVMakeCompressibleOptPass());
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}
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@ -143,27 +143,27 @@ define dso_local i32 @branch_in_branch(i32 noundef %dim) local_unnamed_addr {
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; VENTUS-NEXT: li t1, 14
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; VENTUS-NEXT: vmv.v.x v1, t1
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; VENTUS-NEXT: vmv.v.x v0, t0
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; VENTUS-NEXT: regext zero, zero, 8
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; VENTUS-NEXT: .Lpcrel_hi4:
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; VENTUS-NEXT: auipc t1, %pcrel_hi(.LBB2_7)
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; VENTUS-NEXT: setrpc zero, t1, %pcrel_lo(.Lpcrel_hi4)
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; VENTUS-NEXT: regext zero, zero, 8
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; VENTUS-NEXT: vblt v33, v1, .LBB2_7
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; VENTUS-NEXT: # %bb.1: # %if.else
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; VENTUS-NEXT: li t0, 17
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; VENTUS-NEXT: vmv.v.x v0, t0
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; VENTUS-NEXT: regext zero, zero, 64
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; VENTUS-NEXT: .Lpcrel_hi5:
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; VENTUS-NEXT: auipc t1, %pcrel_hi(.LBB2_7)
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; VENTUS-NEXT: setrpc zero, t1, %pcrel_lo(.Lpcrel_hi5)
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; VENTUS-NEXT: regext zero, zero, 64
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; VENTUS-NEXT: vbltu v0, v33, .LBB2_4
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; VENTUS-NEXT: # %bb.2: # %if.then2
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; VENTUS-NEXT: li t0, 1
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; VENTUS-NEXT: vmv.v.x v0, t0
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; VENTUS-NEXT: call _Z13get_global_idj
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; VENTUS-NEXT: regext zero, zero, 64
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; VENTUS-NEXT: .Lpcrel_hi6:
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; VENTUS-NEXT: auipc t1, %pcrel_hi(.LBB2_6)
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; VENTUS-NEXT: setrpc zero, t1, %pcrel_lo(.Lpcrel_hi6)
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; VENTUS-NEXT: regext zero, zero, 64
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; VENTUS-NEXT: vblt v0, v33, .LBB2_5
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; VENTUS-NEXT: # %bb.3: # %if.then2
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; VENTUS-NEXT: li t0, 23
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