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444602 Commits

Author SHA1 Message Date
zhoujing 940da111a3 [VENTUS][RISCV][fix] Fix divergent analysis bug for store node 2023-06-12 14:50:55 +08:00
zhoujing c60810b243 [VENTUS][RISCV][feat] Modify SP stack size calculation 
Add initial SP stack size calculation support, still remains many issues
 2023-06-12 13:27:55 +08:00
zhoujing a38d49bf2e [VENTUS][RISCV][readme] Update declaration of developer for Ventus compiler 2023-06-12 10:19:11 +08:00
zhoujing faf6a0bcd9 [VENTUS][RISCV][fix] Add initial Tp stack size calculation 
Cause there are two stacks in Ventus, we need to seperate TP stack and SP stack,
this commit just add very initial support for TP stack size calculation
 2023-06-11 12:18:39 +08:00
zhoujing 180b3d4429 [VENTUS][RISCV][feat] Add VGPRSpill stack id for ventus 
There are two stacks in ventus for registers spill, SGPRSpill and VGPRSpill,
SGPRSpill is for global/constant memory related GPR registers spill, VGPRSpill
is for private/shared memory related VGPR registers spill
 2023-06-07 11:57:20 +08:00
zhoujing 8a99697480 [VENTUS][RISCV][readme] Update copyright 2023-06-06 09:12:20 +08:00
zhoujing 033505de1d [VENTUS][RISCV][fix] Modify calling convention 2023-06-05 17:11:25 +08:00
zhoujing 967cb725c8 [VENTUS][RISCV][feat] Set ventus kernel for OpenCL kernel functions 2023-06-05 13:10:35 +08:00
zhoujingya 3fdda4cd8e [VENTUS][RISCV][feat] Add script which will be used by pocl when using ventus compiler 2023-05-31 13:15:34 +08:00
zhoujing 8e86eb368c [VENTUS][RISCV][workflow] Modify workflow script 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-31 12:03:02 +08:00
zhoujing 7d66e05b28 [VENTUS][RISCV][fix] Fix insert join instructions pass bug 
After this fix, the vbeq/join instructions codegen are normal now

Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-31 12:02:27 +08:00
zhoujing 9b3f6791f7 [VENTUS][RISCV][workflow] Update workflow 
THis update is due to related repositories' update

Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-31 12:01:50 +08:00
yangkex 4e3ea6bb32 [VENTUS][RISCV][doc] Update README.md 
add packages needed for other repositories and modify branch for driver-repository.

Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-31 12:00:45 +08:00
zhoujing 8c7f5a3c28 [VENTUS][RISCV][fix] Fix instructuions which contain 5 bits unsigned immediate asmParser && pattern bug 2023-05-26 17:52:36 +08:00
zhoujing b22d7bd36f [VENTUS][RISCV][fix] Fix vlw/vsw instructions' pattern 2023-05-26 11:12:48 +08:00
zhoujing 00354e37b9 [VENTUS][RISCV][NFC] Just modify the build script 2023-05-25 16:41:56 +08:00
zhoujing a47a105986 [VENTUS][RISCV][doc] Update README.md 2023-05-25 16:41:38 +08:00
zhoujing a17f01270b [VENTUS][RISCV][fix] Fix vlw12.v/vsw12.v instructions' codegen pattern 
Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-05-25 14:49:48 +08:00
zhoujingya ad23baaa51 [VENTUS][RISCV][feat] Add more floating point instructions pattern 
Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-05-25 14:48:30 +08:00
zhoujing 5d29133ab0 [VENTUS][RISCV][fix] Add isReturn block check before insertation 2023-05-25 14:09:12 +08:00
zhoujingya 2a65cb7c85 [VENTUS][RISCV][workflow] Add spike and driver building process to workflow 
We need spike && hardware driver to test the functionality of software, Adding
this to workflow is benificial for testing
 2023-05-17 09:19:18 +08:00
zhoujingya c0cdbbc172 [VENTUS][RISCV][style] Formatting && Change function and variable names 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-12 17:41:45 +08:00
zhoujingya 961d5a6b42 [VENTUS][RISCV][fix] Uncomment missing assertation 2023-05-12 14:46:27 +08:00
zhoujingya 97a3f99e4c [VENTUS][RISCV][pass] Add insert join instruction pass for VBranch 
we follow the following rules to insert join block and join instruction

 1: Legalize all the return block
    when there are one more return blocks in machine function, there must be
    branches, we need to reduce return blocks number down to 1
 1.1: If two return blocks have common nearest parent branch, this two blocks
    need to be joined, and we add a hasBeenJoined marker for this parent
    branch
 1.2: after we complete 1.1 process, there maybe one more return blocks, we
    need to further add join block, we recursively build dominator tree for
    these return blocks, first we find the nearest common dominator branch for
    two return blocks, and then get dominator tree path between dominator
    and each return block, we need to check this path in which whether any
    other branch blocks exists, ideally, the branch block in path should have
    been joined and marked, if not, this path is illegal, these two block can
    not be joined

 2: Insert join instructions
 2.1: we scan through the MachineBasic blocks and check what blocks to insert
    join instruction, below MBB represents MachineBasic Block
 2.2: The MBB must have one more predecessors and its nearest dominator must
     be a VBranch
 2.3: Then we analyze the the predecessor of MBB, if the predecessor
    has single successor, we add a join instruction to the predecessor end,
    other wise, we need to insert a join block between predecessor and MBB
 2023-05-12 14:01:57 +08:00
zhoujingya a0a80bfdad [VENTUS][RISCV][fix] Fix BUILD_TYPE variable setting error 2023-05-09 17:14:38 +08:00
zhoujingya 724033f20a [VENTUS][RISCV][feat] Add exception handler to stop spike in crt0.s 2023-04-27 10:19:21 +08:00
zhoujingya 5f776bde21 [VENTUS][RISCV][fix] Constraint divergent private load/store instructions can only use tp register 2023-04-27 09:32:25 +08:00
zhoujingya 0e9d5763ed [VENTUS][RISCV][feat] Add print buffer size and address initialization in crt0.s 2023-04-26 14:39:00 +08:00
zhoujingya 7ef089a734 [VENTUS][RISCV][github action] Add customized action for ventus 2023-04-25 13:15:04 +08:00
zhoujingya ea75d078fb [VENTUS][RISCV][feat] Add zfinx support 
Because there is no `F` extension and float registers in ventus, we need to
support `zfinx` to generate common float instructions
 2023-04-23 11:29:09 +08:00
zhoujingya 9d9283fa7b [VENTUS][RISCV][fix] Fix ventus abi and calling convention 
Kernel functions use sp as GPRs spill stack slots
Non-kernel functions use tp as VGPRs spill stack slots
 2023-04-20 15:27:52 +08:00
yangkex 39f0a4090c [VENTUS][RISCV][fix] Fix tp initial value bugs 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-04-19 12:38:53 +08:00
zhoujingya f28e6c5e38 [VENTUS][RISCV][feat] Add vararg backend support in ventus 
We adjust the stack growing direction early months for OpenCL, in order to be
compatible with current architecture, we need to do some modification to
support vararg
 2023-04-18 10:03:53 +08:00
zhoujingya b01963690d [VENTUS][RISCV][fix] Fix vsw/vlw encoding bugs and update test cases 
Fix vlw/vsw instructions' encoding since them have been updated
 2023-04-17 18:07:33 +08:00
zhoujingya 8ba248d102 [VENTUS][RISCV] Add vararg support 
Because ventus riscv is designed specially for OpenCL language, we originally add or remove some language features mainly for serving OpenCL, but we now need to add customized `printf` function which is expected to be written in C, so we need also to add support for C language features in current ventus

Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-04-13 15:00:35 +08:00
zhoujingya 0642d65513 Add align to section .tohost && add section _end and _edata 2023-03-31 11:35:31 +08:00
zhoujingya b6f68623af Format and typo fixes in README 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-03-30 18:10:24 +08:00
zhoujingya 980634ce54 Update README.md for how to use compiler to generate ELF 2023-03-30 17:43:10 +08:00
zhoujingya 7dc6ac967f Add customized linker script for ventus * Original linker script is from zcc build-system, we just make some modification 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-03-30 17:42:07 +08:00
zhoujingya ba03b01b03 Update function comment for get_global_id(x/y/z) 2023-03-30 16:20:19 +08:00
yangkex 513e9eb8d9 set mstatus in crt0.S to enable F extension 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-03-30 14:19:00 +08:00
zhoujingya 569cd01769 Fix get_global_id bug 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-03-30 11:43:28 +08:00
zhoujingya 0616b958b2 Add jump to spike_end instruction in crt0 && Run clean before building libclc 2023-03-30 11:18:29 +08:00
zhoujingya 458808b5d1 Remove FeatureStdExtC in ventus 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-03-30 10:14:52 +08:00
zhoujingya c459a33bb8 Add vsetvli instruction in crt0 && remove barrier headers in libclc 2023-03-29 21:42:44 +08:00
zhoujingya ea14d5f074 Update build-ventus.sh for checking ocl-icd is built or not before building pocl 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-03-29 09:20:24 +08:00
zhoujingya 530939a01b Modify kernel entry since CSR_KNL is ready in spike 2023-03-28 17:05:28 +08:00
zhoujingya 625746818d Fix vlw12/vsw12 assembly code generation bugs * Before: vsw12.v v1, zero(v0) * After: vsw12.v v1, 0(v0) 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-03-28 13:49:47 +08:00
zhoujingya 2b54041ac3 Fix encoding bug for endprg&vmx.v.x&barrier 2023-03-27 17:44:38 +08:00
zhoujingya 80a5b3e868 [Jenkins] Add label 2023-03-24 17:46:11 +08:00