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AsmParser
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[VENTUS][fix] Remove instructions not supported by hardware
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2023-11-24 17:26:50 +08:00 |
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Disassembler
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[VENTUS][fix] Add a switch to the C extension
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2024-05-14 17:26:24 +08:00 |
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GISel
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[RISCV] Move GlobalISEL specific files to sub-directory [nfc]
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2022-11-15 14:24:50 -08:00 |
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MCTargetDesc
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[VENTUS][fix] Fix memory flags set in tablegen #129
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2024-06-24 23:01:47 +08:00 |
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TargetInfo
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[RISCV] Re-enable JIT support
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2022-08-11 11:41:02 +02:00 |
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CMakeLists.txt
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[VENTUS][Printf] Add opencl printf pass
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2025-02-12 11:01:04 +08:00 |
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RISCV.h
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[VENTUS][Printf] Add opencl printf pass
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2025-02-12 11:01:04 +08:00 |
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RISCV.td
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Remove FeatureStdExtC in ventus
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2023-03-30 10:14:52 +08:00 |
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RISCVAsmPrinter.cpp
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Merge pull request #70 from THU-DSP-LAB/resource_manage
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2024-02-01 13:17:45 +08:00 |
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RISCVCallingConv.td
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…
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RISCVCodeGenPrepare.cpp
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[RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool.
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2022-08-12 22:21:05 -07:00 |
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RISCVExpandAtomicPseudoInsts.cpp
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[VENTUS][fix] Comment out illegal fmv.w.x instruction and change vmv instructions' format
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2023-10-09 14:04:55 +08:00 |
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RISCVExpandPseudoInsts.cpp
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[VENTUS][fix] Fix regexti instruction bug
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2025-03-10 11:30:11 +08:00 |
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RISCVFrameLowering.cpp
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[VENTUS][fix] Put local variables declared in kernel function into shared memory
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2024-03-05 16:32:59 +08:00 |
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RISCVFrameLowering.h
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[patch] Add a fix patch from terapines_dev branch
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2024-03-08 18:23:47 +08:00 |
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RISCVISelDAGToDAG.cpp
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[patch] Add a fix patch from terapines_dev branch
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2024-03-08 18:23:47 +08:00 |
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RISCVISelDAGToDAG.h
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[VENTUS][RISCV] Fix VBranch instruction info and select codegen patterns.
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2023-06-27 11:12:37 +08:00 |
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RISCVISelLowering.cpp
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[VENTUS][NFC] Remove invalid code about divergence
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2025-03-07 11:04:28 +08:00 |
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RISCVISelLowering.h
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[VENTUS][fix]Assign initial value for VastartStoreFrameIndex
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2024-05-15 13:39:07 +08:00 |
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RISCVInstrFormats.td
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[VENTUS][fix] Add memory access flags in tablegen
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2024-06-14 09:46:00 +08:00 |
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RISCVInstrFormatsC.td
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…
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RISCVInstrFormatsV.td
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[RISCV] Replace hardcoded constant with OPIVI.Value in tablegen. NFC
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2022-11-30 20:58:40 -08:00 |
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RISCVInstrInfo.cpp
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[VENTUS][fix] Add memory access flags in tablegen
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2024-06-14 09:46:00 +08:00 |
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RISCVInstrInfo.h
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[VENTUS][fix] Put local variables declared in kernel function into shared memory
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2024-03-05 16:32:59 +08:00 |
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RISCVInstrInfo.td
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[VENTUS][RISCV][fix] Constraint divergent private load/store instructions can only use tp register
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2023-04-27 09:32:25 +08:00 |
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RISCVInstrInfoA.td
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[RISCV] Add target feature to force-enable atomics
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2022-08-09 16:04:46 +02:00 |
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RISCVInstrInfoC.td
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Add MC support of RISCV Zcd Extension
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2022-11-24 05:48:06 +08:00 |
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RISCVInstrInfoD.td
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Propagate uniform execution predicates to all Ventus sALU operations.
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2022-12-16 14:04:55 +08:00 |
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RISCVInstrInfoF.td
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Update customized instructions' encoding
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2023-02-24 11:21:19 +08:00 |
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RISCVInstrInfoM.td
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…
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RISCVInstrInfoV.td
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[VENTUS][RISCV][test&fix] Add more MC test and fix related bugs
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2023-07-11 11:17:55 +08:00 |
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RISCVInstrInfoVPseudos.td
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[RISCV][Codegen] Account for LMUL in Vector floating-point instructions
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2022-11-30 11:09:21 -08:00 |
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RISCVInstrInfoVSDPatterns.td
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[RISCV] Use _TIED form of VFWADD(U)_WV/VFWSUB(U)_WV to avoid early clobber.
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2022-10-03 21:44:08 -07:00 |
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RISCVInstrInfoVVLPatterns.td
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[VP][RISCV] Add vp.nearbyint and RISC-V support.
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2022-11-16 14:05:35 +08:00 |
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RISCVInstrInfoXVentana.td
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[RISCV] Implement assembler support for XVentanaCondOps
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2022-11-14 09:01:54 -08:00 |
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RISCVInstrInfoZb.td
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[VENTUS][RISCV] Fix rd,rs1,rs2,rs3 register ordering in regext insertion pass.
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2023-07-06 11:47:34 +08:00 |
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RISCVInstrInfoZfh.td
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Propagate uniform execution predicates to all Ventus sALU operations.
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2022-12-16 14:04:55 +08:00 |
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RISCVInstrInfoZicbo.td
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[VENTUS][RISCV] Fix rd,rs1,rs2,rs3 register ordering in regext insertion pass.
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2023-07-06 11:47:34 +08:00 |
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RISCVInstrInfoZk.td
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…
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RISCVMCInstLower.cpp
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Very very early step to remove RVV features from code base.
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2022-12-16 17:33:54 +08:00 |
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RISCVMachineFunctionInfo.cpp
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Update Ventus GPGPU ABI: X4 as stack pointer, V0-V31 as arguments registers etc
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2022-12-28 13:11:22 +08:00 |
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RISCVMachineFunctionInfo.h
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[VENTUS][RISCV][fix] Modify calling convention
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2023-06-05 17:11:25 +08:00 |
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RISCVMacroFusion.cpp
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[RISCV] Be more strict about LUI+ADDI macrofusion pre-RA.
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2022-08-21 10:58:15 -07:00 |
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RISCVMacroFusion.h
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…
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RISCVMakeCompressible.cpp
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[VENTUS][fix] Remove instructions not supported by hardware
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2023-11-24 17:26:50 +08:00 |
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RISCVMergeBaseOffset.cpp
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[VENTUS][fix] Remove instructions not supported by hardware
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2023-11-24 17:26:50 +08:00 |
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RISCVRedundantCopyElimination.cpp
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[RISCV] Use analyzeBranch in RISCVRedundantCopyElimination.
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2022-08-29 09:05:53 -07:00 |
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RISCVRegisterInfo.cpp
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[Ventus][fix]Fix missing vmv instruction for FrameReg in divergent path
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2024-06-06 16:16:57 +08:00 |
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RISCVRegisterInfo.h
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[VENTUS][fix]Fix kernel divergent analysis
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2024-04-22 15:53:36 +08:00 |
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RISCVRegisterInfo.td
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[RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI
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2022-08-24 14:16:20 +00:00 |
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RISCVSExtWRemoval.cpp
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[VENTUS][fix] Comment out illegal fmv.w.x instruction and change vmv instructions' format
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2023-10-09 14:04:55 +08:00 |
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RISCVSchedRocket.td
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[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
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2022-10-28 11:57:33 -07:00 |
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RISCVSchedSiFive7.td
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[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
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2022-10-28 11:57:33 -07:00 |
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RISCVSchedule.td
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[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
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2022-10-28 11:57:33 -07:00 |
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RISCVScheduleV.td
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[RISCV][Codegen] Account for LMUL in Vector floating-point instructions
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2022-11-30 11:09:21 -08:00 |
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RISCVScheduleZb.td
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[RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC
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2022-09-23 21:38:42 -07:00 |
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RISCVSearchableTables.td
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Drafting divergent related code, not working yet.
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2022-12-19 18:11:34 +08:00 |
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RISCVSubtarget.cpp
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Very very early step to remove RVV features from code base.
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2022-12-16 17:33:54 +08:00 |
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RISCVSubtarget.h
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[VENTUS][fix] Distinguish the resource usage of each kernel function
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2023-12-14 17:18:20 +08:00 |
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RISCVSystemOperands.td
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[VENTUS][RISCV] Fix insert setrpc/join instruction pass for VBranch.
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2023-06-27 16:02:01 +08:00 |
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RISCVTargetMachine.cpp
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[VENTUS][fix] disable BranchFolderPass, MachineBlockPlacement pass and remove checkJoinMBB from Insert-join-to-VBranch pass
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2025-04-02 10:14:05 +08:00 |
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RISCVTargetMachine.h
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[VENTUS][Printf] Add opencl printf pass
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2025-02-12 11:01:04 +08:00 |
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RISCVTargetObjectFile.cpp
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…
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RISCVTargetObjectFile.h
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…
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RISCVTargetTransformInfo.cpp
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[VENTUS][NFC] Remove invalid code about divergence
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2025-03-07 11:04:28 +08:00 |
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RISCVTargetTransformInfo.h
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[VENTUS][RISCV][fix] Add more divergence ananlysis
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2023-06-15 22:34:40 +08:00 |
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VentusCallingConv.td
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[Ventus] ABI and stack adjustment.
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2023-06-21 13:08:02 +08:00 |
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VentusInsertJoinToVBranch.cpp
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[VENTUS][fix] disable BranchFolderPass, MachineBlockPlacement pass and remove checkJoinMBB from Insert-join-to-VBranch pass
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2025-04-02 10:14:05 +08:00 |
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VentusInstrFormatsV.td
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[VENTUS][fix] Support the regexti instruction
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2024-01-23 09:59:51 +08:00 |
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VentusInstrInfo.td
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[VENTUS][fix] Fix memory flags set in tablegen #129
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2024-06-24 23:01:47 +08:00 |
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VentusInstrInfoA.td
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[VENTUS][RISCV][feat] Add atomic instructions VGPR index support
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2023-07-24 13:38:42 +08:00 |
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VentusInstrInfoC.td
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[VENTUS][RISCV][feat] Add zfinx support
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2023-04-23 11:29:09 +08:00 |
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VentusInstrInfoF.td
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[Ventus][fix] Fix flw/fsw instruction pattern
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2024-08-20 09:59:25 +08:00 |
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VentusInstrInfoM.td
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Propagate uniform execution predicates to all Ventus sALU operations.
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2022-12-16 14:04:55 +08:00 |
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VentusInstrInfoV.td
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[VENTUS][fix] Fix memory flags set in tablegen #129
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2024-06-24 23:01:47 +08:00 |
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VentusInstrInfoVPseudos.td
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[VENTUS][fix] Deprecating vmv.s.x and use vmv.v.x instead
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2023-08-01 13:25:24 +08:00 |
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VentusInstrInfoVSDPatterns.td
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Copy RVV codegen pattern related file RISCVInstrInfo*.td to VentusInstrInfo*.td.
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2022-12-15 17:04:09 +08:00 |
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VentusInstrInfoVVLPatterns.td
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Copy RVV codegen pattern related file RISCVInstrInfo*.td to VentusInstrInfo*.td.
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2022-12-15 17:04:09 +08:00 |
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VentusLegalizeLoad.cpp
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[VENTUS][NFC] Update comments
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2023-09-07 22:18:13 +08:00 |
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VentusPrintfRuntimeBinding.cpp
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[VENTUS][Printf] Add opencl printf pass
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2025-02-12 11:01:04 +08:00 |
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VentusProgramInfo.h
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[VENTUS][fix] Distinguish the resource usage of each kernel function
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2023-12-14 17:18:20 +08:00 |
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VentusRegextInsertion.cpp
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[VENTUS][fix]Fix missing regext instruction for vmsle instruction
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2024-05-21 17:09:48 +08:00 |
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VentusRegisterInfo.td
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[VENTUS][fix]Fix kernel divergent analysis
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2024-04-22 15:53:36 +08:00 |
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VentusVVInstrConversion.cpp
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[VENTUS][RISCV][NFC] Disable conversion for floating VV instrcution convertion
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2023-06-29 14:28:02 +08:00 |
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