zhoujingya aeee8ee171 [VENTUS][fix] Fix memory flags set in tablegen #129 ... In previous logic ,default memory access flag is 0b00, this will cause all no-local/no-private related instructions return true when fall into `RISCVInstrInfo::isUniformMemoryAccess` logic		2024-06-24 23:01:47 +08:00
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CMakeLists.txt	…
RISCVAsmBackend.cpp	[MC] llvm::Optional => std::optional	2022-12-04 21:36:08 +00:00
RISCVAsmBackend.h	[MC] llvm::Optional => std::optional	2022-12-04 21:36:08 +00:00
RISCVBaseInfo.cpp	Fix build error. Now we can have initial divergent execution code generated as expected.	2022-12-20 09:41:21 +08:00
RISCVBaseInfo.h	[VENTUS][fix] Fix memory flags set in tablegen #129	2024-06-24 23:01:47 +08:00
RISCVELFObjectWriter.cpp	[RISCV] Assemble `call foo` to R_RISCV_CALL_PLT	2022-09-13 18:47:55 -07:00
RISCVELFStreamer.cpp	[RISCV] Support .variant_cc directive for the assembler.	2022-12-05 12:13:43 +08:00
RISCVELFStreamer.h	[RISCV] Support .variant_cc directive for the assembler.	2022-12-05 12:13:43 +08:00
RISCVFixupKinds.h	…
RISCVInstPrinter.cpp	Turn on ABI register naming	2023-01-03 11:36:49 +08:00
RISCVInstPrinter.h	…
RISCVMCAsmInfo.cpp	…
RISCVMCAsmInfo.h	…
RISCVMCCodeEmitter.cpp	[VENTUS][workaround] Fix flw/fsw assembly errors	2024-04-26 15:14:22 +08:00
RISCVMCExpr.cpp	…
RISCVMCExpr.h	…
RISCVMCObjectFileInfo.cpp	[RISCV] Add CodeGen support and MC testcase of RISCV Zca Extension	2022-11-22 17:22:26 +08:00
RISCVMCObjectFileInfo.h	…
RISCVMCTargetDesc.cpp	Update Ventus GPGPU ABI: X4 as stack pointer, V0-V31 as arguments registers etc	2022-12-28 13:11:22 +08:00
RISCVMCTargetDesc.h	…
RISCVMatInt.cpp	[RISCV] Use findFirstSet instead of countTrailingZeros. NFC	2022-12-04 18:00:36 -08:00
RISCVMatInt.h	…
RISCVTargetStreamer.cpp	[RISCV] Support .variant_cc directive for the assembler.	2022-12-05 12:13:43 +08:00
RISCVTargetStreamer.h	[RISCV] Support .variant_cc directive for the assembler.	2022-12-05 12:13:43 +08:00