467 lines
16 KiB
C++
467 lines
16 KiB
C++
//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expands pseudo instructions into target
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// instructions. This pass should be run after register allocation but before
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// the post-regalloc scheduling pass.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVInstrInfo.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/MC/MCContext.h"
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using namespace llvm;
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#define RISCV_EXPAND_PSEUDO_NAME "RISCV pseudo instruction expansion pass"
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#define RISCV_PRERA_EXPAND_PSEUDO_NAME \
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"RISCV Pre-RA pseudo instruction expansion pass"
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namespace {
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class RISCVExpandPseudo : public MachineFunctionPass {
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public:
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const RISCVInstrInfo *TII;
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static char ID;
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RISCVExpandPseudo() : MachineFunctionPass(ID) {
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initializeRISCVExpandPseudoPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
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private:
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bool expandMBB(MachineBasicBlock &MBB);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandBarrier(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandCompareSelect(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandVIIMM11(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
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};
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char RISCVExpandPseudo::ID = 0;
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bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
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bool Modified = false;
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for (auto &MBB : MF)
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Modified |= expandMBB(MBB);
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return Modified;
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}
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bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= expandMI(MBB, MBBI, NMBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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// TODO: Expand macro instruction with more than 32 registers here?
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bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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// RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
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// expanded instructions for each pseudo is correct in the Size field of the
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// tablegen definition for the pseudo.
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if (RISCVII::isVOPIMM11(MBBI->getDesc().TSFlags))
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return expandVIIMM11(MBB, MBBI);
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switch (MBBI->getOpcode()) {
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case RISCV::PseudoCCMOVGPR:
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return expandCCOp(MBB, MBBI, NextMBBI);
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case RISCV::PseudoBarrier:
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case RISCV::PseudoSubGroupBarrier:
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return expandBarrier(MBB, MBBI, NextMBBI);
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case RISCV::PseudoVMSLTU_VI:
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case RISCV::PseudoVMSLT_VI:
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case RISCV::PseudoVMSGE_VI:
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case RISCV::PseudoVMSGEU_VI:
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return expandCompareSelect(MBB, MBBI, NextMBBI);
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}
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return false;
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}
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bool RISCVExpandPseudo::expandVIIMM11(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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const TargetRegisterInfo *TRI =
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MBB.getParent()->getSubtarget().getRegisterInfo();
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const MCInstrDesc *MCID = nullptr;
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switch (MBBI->getOpcode()) {
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default:
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llvm_unreachable("Please add IMM11 Pseudo case here!");
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case RISCV::PseudoVOR_VI_IMM11:
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MCID = &TII->get(RISCV::VOR_VI);
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break;
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case RISCV::PseudoVXOR_VI_IMM11:
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MCID = &TII->get(RISCV::VXOR_VI);
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break;
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case RISCV::PseudoVRSUB_VI_IMM11:
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MCID = &TII->get(RISCV::VRSUB_VI);
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break;
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case RISCV::PseudoVAND_VI_IMM11:
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MCID = &TII->get(RISCV::VAND_VI);
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break;
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case RISCV::PseudoVMSNE_VI_IMM11:
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MCID = &TII->get(RISCV::VMSNE_VI);
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break;
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case RISCV::PseudoVMSEQ_VI_IMM11:
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MCID = &TII->get(RISCV::VMSEQ_VI);
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break;
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}
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assert(MCID && "Unexpected opcode");
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MBBI->setDesc(*MCID);
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int64_t Imm = 0;
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signed LowImm = 0;
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signed HighImm = 0;
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unsigned uImm = 0;
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signed Offsets = 0;
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for (unsigned i = 0; i < MBBI->getNumOperands(); ++i) {
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MachineOperand &Op = MBBI->getOperand(i);
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if (Op.isImm()) {
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Imm = Op.getImm();
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assert((Imm <= 1023 && Imm >= -1024) && "imm not in Imm11 range!");
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uImm = Imm & 0x7FF;
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unsigned uLowImm = uImm & 0x1F;
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if (uLowImm & 0x10) {
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if (uLowImm == 0x10) {
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LowImm = -16;
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} else {
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LowImm = -(((~uLowImm) + 1) & 0x1F);
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}
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} else {
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LowImm = uLowImm;
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}
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unsigned uHighImm = (uImm >> 5) & 0x3F;
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if (uHighImm & 0x20) {
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if (uHighImm == 0x20) {
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HighImm = -32;
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} else {
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HighImm = -(((~uHighImm) + 1) & 0x3F);
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}
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} else {
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HighImm = uHighImm;
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}
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Op.ChangeToImmediate(LowImm);
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continue;
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}
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if (!Op.isReg() ||
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MBBI->getDesc().getOperandConstraint(i, MCOI::TIED_TO) != -1)
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continue;
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// deal with register numbers larger than 32.
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if (Op.isReg() &&
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MBBI->getDesc().getOperandConstraint(i, MCOI::TIED_TO) == -1) {
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uint16_t RegEncodingValue = TRI->getEncodingValue(Op.getReg());
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if (RegEncodingValue > 31) {
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int Pos = MBBI->getDesc().getOperandConstraint(i, MCOI::CUSTOM);
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assert(Pos != -1 && "Out of range[0, 31] register operand custom "
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"constraint that must be present.");
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assert(Pos != 1 && Pos != 3 && "Unexpected Pos!");
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Offsets |= (RegEncodingValue >> 5 & 0x7) << (3 * (Pos == 2 ? 1 : Pos));
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}
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}
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}
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DebugLoc DL = MBBI->getDebugLoc();
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// Create instruction to expand imm5 or register basic offset as imm * 32.
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BuildMI(MBB, MBBI, DL, TII->get(RISCV::REGEXTI), RISCV::X0)
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.addReg(RISCV::X0)
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.addImm((HighImm << 6) | Offsets);
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return true;
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}
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bool RISCVExpandPseudo::expandBarrier(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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assert((MBBI->getOpcode() == RISCV::PseudoBarrier ||
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MBBI->getOpcode() == RISCV::PseudoSubGroupBarrier) &&
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"Unexpected opcode");
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bool isBarrier = MBBI->getOpcode() == RISCV::PseudoBarrier;
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unsigned BarrierOpcode = isBarrier ? RISCV::BARRIER : RISCV::SUBGROUP_BARRIER;
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uint32_t MemFlag = MBBI->getOperand(0).getImm();
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// when use barriersub, MemScope is default to be 0
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uint32_t MemScope = isBarrier ? MBBI->getOperand(1).getImm() : 0;
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BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(BarrierOpcode))
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.addImm((MemScope << 3) + MemFlag);
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MBBI->eraseFromParent();
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return true;
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}
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bool RISCVExpandPseudo::expandCompareSelect(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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unsigned Opcode = MBBI->getOpcode();
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if (Opcode == RISCV::PseudoVMSLT_VI) {
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Opcode = RISCV::VMSLE_VI;
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} else if (Opcode == RISCV::PseudoVMSLTU_VI) {
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Opcode = RISCV::VMSLEU_VI;
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} else if (Opcode == RISCV::PseudoVMSGE_VI) {
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Opcode = RISCV::VMSGT_VI;
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} else if (Opcode == RISCV::PseudoVMSGEU_VI) {
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Opcode = RISCV::VMSGTU_VI;
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} else {
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llvm_unreachable("Unexpected Opcode!");
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}
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BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode),
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MBBI->getOperand(0).getReg())
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.addReg(MBBI->getOperand(1).getReg())
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.addImm(MBBI->getOperand(2).getImm() - 1);
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MBBI->eraseFromParent();
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return true;
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}
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bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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assert(MBBI->getOpcode() == RISCV::PseudoCCMOVGPR && "Unexpected opcode");
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
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MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
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MF->insert(++MBB.getIterator(), TrueBB);
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MF->insert(++TrueBB->getIterator(), MergeBB);
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// We want to copy the "true" value when the condition is true which means
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// we need to invert the branch condition to jump over TrueBB when the
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// condition is false.
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auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
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CC = RISCVCC::getOppositeBranchCondition(CC);
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// Insert branch instruction.
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BuildMI(MBB, MBBI, DL, TII->getBrCond(CC))
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.addReg(MI.getOperand(1).getReg())
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.addReg(MI.getOperand(2).getReg())
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.addMBB(MergeBB);
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Register DestReg = MI.getOperand(0).getReg();
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assert(MI.getOperand(4).getReg() == DestReg);
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// Add MV.
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BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
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.add(MI.getOperand(5))
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.addImm(0);
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TrueBB->addSuccessor(MergeBB);
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MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
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MergeBB->transferSuccessors(&MBB);
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MBB.addSuccessor(TrueBB);
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MBB.addSuccessor(MergeBB);
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NextMBBI = MBB.end();
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MI.eraseFromParent();
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// Make sure live-ins are correctly attached to this new basic block.
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LivePhysRegs LiveRegs;
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computeAndAddLiveIns(LiveRegs, *TrueBB);
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computeAndAddLiveIns(LiveRegs, *MergeBB);
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return true;
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}
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class RISCVPreRAExpandPseudo : public MachineFunctionPass {
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public:
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const RISCVInstrInfo *TII;
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static char ID;
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RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {
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initializeRISCVPreRAExpandPseudoPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override {
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return RISCV_PRERA_EXPAND_PSEUDO_NAME;
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}
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private:
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bool expandMBB(MachineBasicBlock &MBB);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandAuipcInstPair(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned FlagsHi, unsigned SecondOpcode);
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bool expandLoadLocalAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandLoadAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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};
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char RISCVPreRAExpandPseudo::ID = 0;
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bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
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bool Modified = false;
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for (auto &MBB : MF)
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Modified |= expandMBB(MBB);
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return Modified;
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}
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bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= expandMI(MBB, MBBI, NMBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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switch (MBBI->getOpcode()) {
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case RISCV::PseudoLLA:
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return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
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case RISCV::PseudoLA:
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return expandLoadAddress(MBB, MBBI, NextMBBI);
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case RISCV::PseudoLA_TLS_IE:
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return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
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case RISCV::PseudoLA_TLS_GD:
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return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
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}
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return false;
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}
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bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
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unsigned SecondOpcode) {
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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Register DestReg = MI.getOperand(0).getReg();
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Register ScratchReg =
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MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
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MachineOperand &Symbol = MI.getOperand(1);
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Symbol.setTargetFlags(FlagsHi);
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MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
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MachineInstr *MIAUIPC =
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BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
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MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
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MachineInstr *SecondMI =
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BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
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.addReg(ScratchReg)
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.addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
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if (MI.hasOneMemOperand())
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SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
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MI.eraseFromParent();
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return true;
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}
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bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
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RISCV::ADDI);
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}
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bool RISCVPreRAExpandPseudo::expandLoadAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineFunction *MF = MBB.getParent();
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assert(MF->getTarget().isPositionIndependent());
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const auto &STI = MF->getSubtarget<RISCVSubtarget>();
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unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
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SecondOpcode);
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}
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bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineFunction *MF = MBB.getParent();
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const auto &STI = MF->getSubtarget<RISCVSubtarget>();
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unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
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SecondOpcode);
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}
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bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
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RISCV::ADDI);
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}
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} // end of anonymous namespace
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INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
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RISCV_EXPAND_PSEUDO_NAME, false, false)
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INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
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RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
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namespace llvm {
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FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
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FunctionPass *createRISCVPreRAExpandPseudoPass() {
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return new RISCVPreRAExpandPseudo();
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}
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} // end of namespace llvm
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