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[VENTUS][fix] Comment out illegal fmv.w.x instruction and change vmv instructions' format 

https://github.com/THU-DSP-LAB/llvm-project/issues/30
This commit is contained in:
zhoujingya 2023-10-09 14:04:55 +08:00
parent 2b376d146a
commit f9a20984b5
9 changed files with 28 additions and 28 deletions
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2
llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
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@ -624,7 +624,6 @@ bool RISCVExpandAtomicPseudo::expandAtomicCmpXchg(
MCRegister VGPR1 = RRI->findUnusedRegister(
MF->getRegInfo(), &RISCV::VGPRRegClass, *MF);
BuildMI(LoopTailMBB, DL, TII->get(RISCV::VMV_V_X), VGPR1)
.addReg(VGPR1)
.addReg(RISCV::X0);
BuildMI(LoopTailMBB, DL, TII->get(RISCV::VBNE))
.addReg(ScratchReg)
@ -660,7 +659,6 @@ bool RISCVExpandAtomicPseudo::expandAtomicCmpXchg(
MCRegister VGPR2 = RRI->findUnusedRegister(
MF->getRegInfo(), &RISCV::VGPRRegClass, *MF);
BuildMI(LoopTailMBB, DL, TII->get(RISCV::VMV_V_X), VGPR2)
.addReg(VGPR2)
.addReg(RISCV::X0);
BuildMI(LoopTailMBB, DL, TII->get(RISCV::VBNE))
.addReg(ScratchReg)

1
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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@ -419,7 +419,6 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
.setMIFlag(MachineInstr::FrameSetup);
BuildMI(MBB, MBBI, DL, TII->get(RISCV::VMV_V_X),
RI->getPrivateMemoryBaseRegister(MF))
.addReg(RI->getPrivateMemoryBaseRegister(MF))
.addReg(TPReg);
}

2
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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@ -1304,7 +1304,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
case RISCV::CTZW:
case RISCV::CPOPW:
case RISCV::SLLI_UW:
case RISCV::FMV_W_X:
// case RISCV::FMV_W_X:
case RISCV::FCVT_H_W:
case RISCV::FCVT_H_WU:
case RISCV::FCVT_S_W:

14
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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@ -24,6 +24,7 @@
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@ -37,11 +38,13 @@
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Support/Alignment.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <optional>
@ -3930,10 +3933,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return Vec;
}
case ISD::LOAD: {
EVT VT = Op.getValueType();
if(VT == MVT::i16) {
errs() << "jjjjj\n";
}
if (auto V = expandUnalignedRVVLoad(Op, DAG))
return V;
if (Op.getValueType().isFixedLengthVector())
@ -6735,7 +6734,7 @@ SDValue RISCVTargetLowering::lowerFixedLengthVectorSelectToRVV(
SDValue RISCVTargetLowering::lowerToPositiveImm(SDValue Op, SelectionDAG &DAG) const {
signed Imm = Op->getConstantOperandVal(1);
SDValue NewConst = DAG.getConstant(-Imm, SDLoc(Op->getOperand(1).getNode()),
SDValue NewConst = DAG.getConstant(-Imm, SDLoc(Op->getOperand(1).getNode()),
Op->getOperand(1).getNode()->getValueType(0));
SDValue NewValue = DAG.getNode(ISD::SUB, SDLoc(Op), Op->getVTList(),
Op->getOperand(0), NewConst);
@ -7481,7 +7480,7 @@ SDValue RISCVTargetLowering::lowerKernargMemParameter(
// alignment than 4, but we don't really need it.
SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset);
SDValue Load = DAG.getLoad(MVT::i32, SL, Chain, Ptr, PtrInfo, Align(4),
MachineMemOperand::MODereferenceable |
MachineMemOperand::MODereferenceable |
MachineMemOperand::MOInvariant);
SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32);
@ -7492,7 +7491,7 @@ SDValue RISCVTargetLowering::lowerKernargMemParameter(
// TODO: Support vector and half type.
//ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg);
return DAG.getMergeValues({ ArgVal, Load.getValue(1) }, SL);
return DAG.getMergeValues({ ArgVal, Load.getValue(1) }, SL);
}
SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, Offset);
@ -11176,7 +11175,6 @@ static MachineBasicBlock *emitFROUND(MachineInstr &MI, MachineBasicBlock *MBB,
Register Dummy = MRI.createVirtualRegister(&RISCV::VGPRRegClass);
Register Dummy1 = MRI.createVirtualRegister(&RISCV::VGPRRegClass);
BuildMI(MBB, DL, TII.get(RISCV::VMV_V_X), Dummy)
.addReg(Dummy, RegState::Undef)
.addReg(RISCV::X0);
BuildMI(MBB, DL, TII.get(RISCV::VADD_VX), Dummy1)
.addReg(Dummy)

1
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
View File

@ -181,7 +181,6 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
if (RISCV::GPRRegClass.contains(SrcReg) &&
RISCV::VGPRRegClass.contains(DstReg)) {
BuildMI(MBB, MBBI, DL, get(RISCV::VMV_V_X), DstReg)
.addReg(DstReg, RegState::Undef)
.addReg(SrcReg, getKillRegState(KillSrc));
return;
}

2
llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
View File

@ -108,7 +108,7 @@ static bool hasAllWUsers(const MachineInstr &OrigMI, MachineRegisterInfo &MRI) {
case RISCV::CPOPW:
case RISCV::SLLI_UW:
case RISCV::FMV_H_X:
case RISCV::FMV_W_X:
// case RISCV::FMV_W_X:
case RISCV::FCVT_H_W:
case RISCV::FCVT_H_WU:
case RISCV::FCVT_S_W:

5
llvm/lib/Target/RISCV/VentusInsertJoinToVBranch.cpp
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@ -227,13 +227,14 @@ bool VentusInsertJoinToVBranch::checkJoinMBB(MachineBasicBlock &MBB) const {
// For some instructions like vmv.v, if the src register are defined in
// all predecessors, then it should not appear after join point
for (auto &MI : make_early_inc_range(MBB)) {
// FIXME: Maybe vfmv.v.f instruction need to be checked too
if (MI.getOpcode() != RISCV::VMV_V_X)
continue;
// To be removed vmv.v instruction flag
bool NeedToBeErased = false;
assert(MI.getOperand(2).isReg() && "unexpected operator");
auto Defines = MR.def_instructions(MI.getOperand(2).getReg());
assert(MI.getOperand(1).isReg() && "unexpected operator");
auto Defines = MR.def_instructions(MI.getOperand(1).getReg());
bool IsInSameBlock = false;
for (auto &Def : Defines) {

14
llvm/lib/Target/RISCV/VentusInstrInfoF.td
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@ -426,8 +426,8 @@ defm FCVT_S_WU : FPUnaryOp_r_frm_m<0b1101000, 0b00001, FXINX, "fcvt.s.wu">,
defm : FPUnaryOpDynFrmAlias_m<FCVT_S_WU, "fcvt.s.wu", FXINX>;
let Predicates = [HasStdExtZfinx], mayRaiseFPException = 0 in
def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, GPRF32, GPR, "fmv.w.x">,
Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
// def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, GPRF32, GPR, "fmv.w.x">,
// Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
defm FCVT_L_S : FPUnaryOp_r_frm_m<0b1100000, 0b00010, XFIN64X, "fcvt.l.s">,
Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>;
@ -535,8 +535,8 @@ class PatFprFprDynFrm<SDPatternOperator OpNode, RVInstRFrm Inst,
let Predicates = [HasStdExtZfinx] in {
/// Float constants
def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>;
def : Pat<(f32 (fpimmneg0)), (FSGNJN_S (FMV_W_X X0), (FMV_W_X X0))>;
// def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>;
// def : Pat<(f32 (fpimmneg0)), (FSGNJN_S (FMV_W_X X0), (FMV_W_X X0))>;
/// Float conversion operations
@ -648,8 +648,8 @@ defm : UniformStPat<store, FSW, GPRF32, f32>;
let Predicates = [HasStdExtZfinx, IsRV32] in {
// Moves (no conversion)
def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>;
def : Pat<(i32 (bitconvert GPRF32:$rs1)), (FMV_X_W GPRF32:$rs1)>;
// def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>;
// def : Pat<(i32 (bitconvert GPRF32:$rs1)), (FMV_X_W GPRF32:$rs1)>;
// float->[u]int. Round-to-zero must be used.
def : Pat<(i32 (UniformUnaryFrag<any_fp_to_sint> GPRF32:$rs1)), (FCVT_W_S $rs1, 0b001)>;
@ -674,7 +674,7 @@ def : Pat<(UniformUnaryFrag<any_uint_to_fp> (i32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b
let Predicates = [HasStdExtZfinx, IsRV64] in {
// Moves (no conversion)
def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>;
// def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>;
def : Pat<(riscv_fmv_x_anyextw_rv64 GPRF32:$src), (FMV_X_W GPRF32:$src)>;
def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 GPRF32:$src), i32),
(FMV_X_W GPRF32:$src)>;

15
llvm/lib/Target/RISCV/VentusInstrInfoV.td
View File

@ -1171,9 +1171,9 @@ let RVVConstraint = NoConstraint in {
def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
(ins VGPR:$vs2), "vmv.x.s", "$vd, $vs2">,
Sched<[WriteVIMovVX, ReadVIMovVX]>;
let Constraints = "$vd = $vd_rb" in
def VMV_V_X : RVInstV2<0b010111, 0b00000, OPIVX, (outs VGPR:$vd),
(ins VGPR:$vd_rb, GPR:$rs1), "vmv.v.x", "$vd, $rs1">,
(ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">,
Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>;
} // RVVConstraint = NoConstraint
@ -1187,9 +1187,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs GPRF32:$vd),
(ins VGPR:$vs2), "vfmv.f.s", "$vd, $vs2">,
Sched<[WriteVFMovVF, ReadVFMovVF]>;
let Constraints = "$vd = $vd_wb" in
def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VGPR:$vd_wb),
(ins VGPR:$vd, GPRF32:$rs1), "vfmv.s.f", "$vd, $rs1">,
def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VGPR:$vd),
(ins GPRF32:$rs1), "vfmv.s.f", "$vd, $rs1">,
Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
@ -1484,3 +1483,9 @@ def : Pat<(XLenVT (DivergentBinFrag<sub> (XLenVT VGPR:$rs1), uimm12:$imm)),
(XLenVT (VSUBIMM12 VGPR:$rs1, uimm12:$imm))>;
def : Pat<(XLenVT (DivergentBinFrag<add> (XLenVT VGPR:$rs1), uimm12:$imm)),
(XLenVT (VADDIMM12 VGPR:$rs1, uimm12:$imm))>;
// There already has patterns defined in VentusInstrInfo.td
let Predicates = [HasStdExtZfinx] in {
def : Pat<(f32 (bitconvert (i32 GPR:$src))), (VMV_V_X GPR:$src)>;
def : Pat<(i32 (bitconvert GPRF32:$src)), (VFMV_V_F GPRF32:$src)>;
} // Predicates = [HasStdExtZfinx]