Propagate uniform execution predicates to all Ventus sALU operations.
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@ -340,11 +340,11 @@ def PseudoFROUND_D : PseudoFROUND<FPR64>;
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/// Loads
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defm : LdPat<load, FLD, f64>;
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defm : UniformLdPat<load, FLD, f64>;
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/// Stores
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defm : StPat<store, FSD, FPR64, f64>;
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defm : UniformStPat<store, FSD, FPR64, f64>;
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/// Pseudo-instructions needed for the soft-float ABI with RV32D
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@ -587,11 +587,11 @@ def PseudoFROUND_S : PseudoFROUND<FPR32>;
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/// Loads
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defm : LdPat<load, FLW, f32>;
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defm : UniformLdPat<load, FLW, f32>;
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/// Stores
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defm : StPat<store, FSW, FPR32, f32>;
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defm : UniformStPat<store, FSW, FPR32, f32>;
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} // Predicates = [HasStdExtF]
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@ -525,8 +525,8 @@ def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>;
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} // Predicates = [HasStdExtZbbOrZbkb]
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let Predicates = [HasStdExtZbbOrZbkb] in {
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def : PatGprGpr<shiftop<rotl>, ROL>;
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def : PatGprGpr<shiftop<rotr>, ROR>;
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def : PatGprGpr<UniformShiftFrag<rotl>, ROL>;
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def : PatGprGpr<UniformShiftFrag<rotr>, ROR>;
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def : PatGprImm<rotr, RORI, uimmlog2xlen>;
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// There's no encoding for roli in the the 'B' extension as it can be
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@ -536,25 +536,25 @@ def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
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} // Predicates = [HasStdExtZbbOrZbkb]
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let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
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def : PatGprGpr<shiftopw<riscv_rolw>, ROLW>;
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def : PatGprGpr<shiftopw<riscv_rorw>, RORW>;
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def : PatGprGpr<UniformShiftWFrag<riscv_rolw>, ROLW>;
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def : PatGprGpr<UniformShiftWFrag<riscv_rorw>, RORW>;
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def : PatGprImm<riscv_rorw, RORIW, uimm5>;
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def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
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(RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
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} // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
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let Predicates = [HasStdExtZbs] in {
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def : Pat<(and (not (shiftop<shl> 1, GPR:$rs2)), GPR:$rs1),
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def : Pat<(and (not (UniformShiftFrag<shl> 1, GPR:$rs2)), GPR:$rs1),
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(BCLR GPR:$rs1, GPR:$rs2)>;
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def : Pat<(and (rotl -2, GPR:$rs2), GPR:$rs1), (BCLR GPR:$rs1, GPR:$rs2)>;
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def : Pat<(or (shiftop<shl> 1, GPR:$rs2), GPR:$rs1),
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def : Pat<(or (UniformShiftFrag<shl> 1, GPR:$rs2), GPR:$rs1),
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(BSET GPR:$rs1, GPR:$rs2)>;
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def : Pat<(xor (shiftop<shl> 1, GPR:$rs2), GPR:$rs1),
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def : Pat<(xor (UniformShiftFrag<shl> 1, GPR:$rs2), GPR:$rs1),
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(BINV GPR:$rs1, GPR:$rs2)>;
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def : Pat<(and (shiftop<srl> GPR:$rs1, GPR:$rs2), 1),
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def : Pat<(and (UniformShiftFrag<srl> GPR:$rs1, GPR:$rs2), 1),
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(BEXT GPR:$rs1, GPR:$rs2)>;
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def : Pat<(shiftop<shl> 1, GPR:$rs2),
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def : Pat<(UniformShiftFrag<shl> 1, GPR:$rs2),
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(BSET X0, GPR:$rs2)>;
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def : Pat<(and GPR:$rs1, BCLRMask:$mask),
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@ -659,7 +659,7 @@ let Predicates = [HasStdExtZbkb, IsRV64] in {
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def : Pat<(i64 (or (zexti32 GPR:$rs1), (shl GPR:$rs2, (i64 32)))),
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(PACK GPR:$rs1, GPR:$rs2)>;
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def : Pat<(binop_allwusers<or> (shl GPR:$rs2, (i64 16)),
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def : Pat<(UniformWBinFrag<or> (shl GPR:$rs2, (i64 16)),
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(zexti16 GPR:$rs1)),
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(PACKW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(i64 (or (sext_inreg (shl GPR:$rs2, (i64 16)), i32),
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@ -344,11 +344,11 @@ def PseudoFROUND_H : PseudoFROUND<FPR16>;
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let Predicates = [HasStdExtZfhOrZfhmin] in {
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/// Loads
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defm : LdPat<load, FLH, f16>;
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defm : UniformLdPat<load, FLH, f16>;
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/// Stores
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defm : StPat<store, FSH, FPR16, f16>;
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defm : UniformStPat<store, FSH, FPR16, f16>;
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/// Float conversion operations
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@ -48,7 +48,7 @@ class UniformTernaryFrag<SDPatternOperator Op> : PatFrag<
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[{ return !N->isDivergent(); }]>;
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class UniformTetradFrag<SDPatternOperator Op> : PatFrag<
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(ops node:$src0, node:$src1, node:$src2, node:$sec3),
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(ops node:$src0, node:$src1, node:$src2, node:$src3),
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(Op $src0, $src1, $src2, $src3),
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[{ return !N->isDivergent(); }]>;
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@ -1418,18 +1418,6 @@ multiclass SelectCC_GPR_rrirr<RegisterClass valty> {
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let Predicates = [NoShortForwardBranchOpt] in
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defm Select_GPR : SelectCC_GPR_rrirr<GPR>;
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class SelectCompressOpt<CondCode Cond>: Pat<(riscv_selectcc_frag:$select GPR:$lhs, simm12_no6:$Constant, Cond,
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GPR:$truev, GPR:$falsev),
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(Select_GPR_Using_CC_GPR (ADDI GPR:$lhs, (NegImm simm12:$Constant)), X0,
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(IntCCtoRISCVCC $select), GPR:$truev, GPR:$falsev)>;
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def OptForMinSize : Predicate<"MF ? MF->getFunction().hasMinSize() : false">;
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let Predicates = [HasStdExtC, OptForMinSize] in {
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def : SelectCompressOpt<SETEQ>;
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def : SelectCompressOpt<SETNE>;
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}
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/// Branches and jumps
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// Match `riscv_brcc` and lower to the appropriate RISC-V branch instruction.
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@ -1441,10 +1429,6 @@ multiclass UniformBccPat<CondCode Cond, RVInstB Inst> {
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(Inst GPR:$rs1, X0, simm13_lsb0:$imm12)>;
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}
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class UniBrccCompressOpt<CondCode Cond, RVInstB Inst> : Pat<
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(UniformTetradFrag<riscv_brcc> GPR:$lhs, simm12_no6:$Constant, Cond, bb:$place),
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(Inst (ADDI GPR:$lhs, (NegImm simm12:$Constant)), X0, bb:$place)>;
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defm : UniformBccPat<SETEQ, BEQ>;
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defm : UniformBccPat<SETNE, BNE>;
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defm : UniformBccPat<SETLT, BLT>;
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@ -1452,11 +1436,6 @@ defm : UniformBccPat<SETGE, BGE>;
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defm : UniformBccPat<SETULT, BLTU>;
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defm : UniformBccPat<SETUGE, BGEU>;
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let Predicates = [HasStdExtC, OptForMinSize] in {
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def : UniBrccCompressOpt<SETEQ, BEQ>;
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def : UniBrccCompressOpt<SETNE, BNE>;
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}
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let isBarrier = 1, isBranch = 1, isTerminator = 1 in
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def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,
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PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>;
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@ -1590,7 +1569,7 @@ def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs
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/// Loads
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multiclass UniformLdPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT> {
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def : Pat<(vt (UniformBinFrag<LoadOp> (AddrRegImm GPR:$rs1, simm12:$imm12))),
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def : Pat<(vt (UniformUnaryFrag<LoadOp> (AddrRegImm GPR:$rs1, simm12:$imm12))),
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(Inst GPR:$rs1, simm12:$imm12)>;
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}
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@ -1605,7 +1584,7 @@ defm : UniformLdPat<zextloadi16, LHU>;
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/// Stores
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multiclass UniformStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
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ValueType vt> {
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ValueType vt> {
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def : Pat<(UniformBinFrag<StoreOp> (vt StTy:$rs2), (AddrRegImm GPR:$rs1, simm12:$imm12)),
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(Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
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}
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@ -1829,7 +1808,7 @@ def : Pat<(UniformWBinFrag<add> GPR:$rs1, (AddiPair:$rs2)),
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//===----------------------------------------------------------------------===//
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include "VentusInstrInfoM.td"
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include "RISCVInstrInfoA.td"
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include "VentusInstrInfoA.td"
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include "RISCVInstrInfoF.td"
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include "RISCVInstrInfoD.td"
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include "VentusInstrInfoC.td"
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@ -0,0 +1,378 @@
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//===-- VentusInstrInfoA.td - Ventus 'A' instructions ------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Ventus instructions from the standard 'A', Atomic
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// Instructions extension.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPRMemZeroOffset:$rs1),
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opcodestr, "$rd, $rs1"> {
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let rs2 = 0;
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}
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multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {
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def "" : LR_r<0, 0, funct3, opcodestr>;
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def _AQ : LR_r<1, 0, funct3, opcodestr # ".aq">;
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def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">;
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def _AQ_RL : LR_r<1, 1, funct3, opcodestr # ".aqrl">;
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}
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let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
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class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
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opcodestr, "$rd, $rs2, $rs1">;
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multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
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def "" : AMO_rr<funct5, 0, 0, funct3, opcodestr>;
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def _AQ : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">;
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def _RL : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">;
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def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
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}
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multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
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ValueType vt = XLenVT> {
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def : Pat<(StoreOp (AddrRegImm GPR:$rs1, simm12:$imm12), (vt StTy:$rs2)),
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(Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtA] in {
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defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
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defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">,
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Sched<[WriteAtomicSTW, ReadAtomicSTW, ReadAtomicSTW]>;
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defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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} // Predicates = [HasStdExtA]
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let Predicates = [HasStdExtA, IsRV64] in {
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defm LR_D : LR_r_aq_rl<0b011, "lr.d">, Sched<[WriteAtomicLDD, ReadAtomicLDD]>;
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defm SC_D : AMO_rr_aq_rl<0b00011, 0b011, "sc.d">,
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Sched<[WriteAtomicSTD, ReadAtomicSTD, ReadAtomicSTD]>;
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defm AMOSWAP_D : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOADD_D : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOXOR_D : AMO_rr_aq_rl<0b00100, 0b011, "amoxor.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOAND_D : AMO_rr_aq_rl<0b01100, 0b011, "amoand.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOOR_D : AMO_rr_aq_rl<0b01000, 0b011, "amoor.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOMIN_D : AMO_rr_aq_rl<0b10000, 0b011, "amomin.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOMAX_D : AMO_rr_aq_rl<0b10100, 0b011, "amomax.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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} // Predicates = [HasStdExtA, IsRV64]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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// Atomic load/store are available under both +a and +force-atomics.
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// Fences will be inserted for atomic load/stores according to the logic in
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// RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
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let Predicates = [HasAtomicLdSt] in {
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defm : UniformLdPat<atomic_load_8, LB>;
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defm : UniformLdPat<atomic_load_16, LH>;
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defm : UniformLdPat<atomic_load_32, LW>;
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defm : AtomicStPat<atomic_store_8, SB, GPR>;
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defm : AtomicStPat<atomic_store_16, SH, GPR>;
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defm : AtomicStPat<atomic_store_32, SW, GPR>;
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}
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let Predicates = [HasAtomicLdSt, IsRV64] in {
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defm : UniformLdPat<atomic_load_64, LD, i64>;
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defm : AtomicStPat<atomic_store_64, SD, GPR, i64>;
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}
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let Predicates = [HasStdExtA] in {
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/// AMOs
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multiclass AMOPat<string AtomicOp, string BaseInst> {
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def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_monotonic"),
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!cast<RVInst>(BaseInst)>;
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def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acquire"),
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!cast<RVInst>(BaseInst#"_AQ")>;
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def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_release"),
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!cast<RVInst>(BaseInst#"_RL")>;
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def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acq_rel"),
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!cast<RVInst>(BaseInst#"_AQ_RL")>;
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def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_seq_cst"),
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!cast<RVInst>(BaseInst#"_AQ_RL")>;
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}
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defm : AMOPat<"atomic_swap_32", "AMOSWAP_W">;
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defm : AMOPat<"atomic_load_add_32", "AMOADD_W">;
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defm : AMOPat<"atomic_load_and_32", "AMOAND_W">;
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defm : AMOPat<"atomic_load_or_32", "AMOOR_W">;
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defm : AMOPat<"atomic_load_xor_32", "AMOXOR_W">;
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defm : AMOPat<"atomic_load_max_32", "AMOMAX_W">;
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defm : AMOPat<"atomic_load_min_32", "AMOMIN_W">;
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defm : AMOPat<"atomic_load_umax_32", "AMOMAXU_W">;
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||||
defm : AMOPat<"atomic_load_umin_32", "AMOMINU_W">;
|
||||
|
||||
def : Pat<(atomic_load_sub_32_monotonic GPR:$addr, GPR:$incr),
|
||||
(AMOADD_W GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
def : Pat<(atomic_load_sub_32_acquire GPR:$addr, GPR:$incr),
|
||||
(AMOADD_W_AQ GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
def : Pat<(atomic_load_sub_32_release GPR:$addr, GPR:$incr),
|
||||
(AMOADD_W_RL GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
def : Pat<(atomic_load_sub_32_acq_rel GPR:$addr, GPR:$incr),
|
||||
(AMOADD_W_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
def : Pat<(atomic_load_sub_32_seq_cst GPR:$addr, GPR:$incr),
|
||||
(AMOADD_W_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
|
||||
/// Pseudo AMOs
|
||||
|
||||
class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch),
|
||||
(ins GPR:$addr, GPR:$incr, ixlenimm:$ordering), []> {
|
||||
let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
let Size = 20 in
|
||||
def PseudoAtomicLoadNand32 : PseudoAMO;
|
||||
// Ordering constants must be kept in sync with the AtomicOrdering enum in
|
||||
// AtomicOrdering.h.
|
||||
def : Pat<(atomic_load_nand_32_monotonic GPR:$addr, GPR:$incr),
|
||||
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 2)>;
|
||||
def : Pat<(atomic_load_nand_32_acquire GPR:$addr, GPR:$incr),
|
||||
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 4)>;
|
||||
def : Pat<(atomic_load_nand_32_release GPR:$addr, GPR:$incr),
|
||||
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 5)>;
|
||||
def : Pat<(atomic_load_nand_32_acq_rel GPR:$addr, GPR:$incr),
|
||||
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 6)>;
|
||||
def : Pat<(atomic_load_nand_32_seq_cst GPR:$addr, GPR:$incr),
|
||||
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 7)>;
|
||||
|
||||
class PseudoMaskedAMO
|
||||
: Pseudo<(outs GPR:$res, GPR:$scratch),
|
||||
(ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$ordering), []> {
|
||||
let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
class PseudoMaskedAMOMinMax
|
||||
: Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
|
||||
(ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$sextshamt,
|
||||
ixlenimm:$ordering), []> {
|
||||
let Constraints = "@earlyclobber $res,@earlyclobber $scratch1,"
|
||||
"@earlyclobber $scratch2";
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
class PseudoMaskedAMOUMinUMax
|
||||
: Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
|
||||
(ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$ordering), []> {
|
||||
let Constraints = "@earlyclobber $res,@earlyclobber $scratch1,"
|
||||
"@earlyclobber $scratch2";
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
class PseudoMaskedAMOPat<Intrinsic intrin, Pseudo AMOInst>
|
||||
: Pat<(intrin GPR:$addr, GPR:$incr, GPR:$mask, timm:$ordering),
|
||||
(AMOInst GPR:$addr, GPR:$incr, GPR:$mask, timm:$ordering)>;
|
||||
|
||||
class PseudoMaskedAMOMinMaxPat<Intrinsic intrin, Pseudo AMOInst>
|
||||
: Pat<(intrin GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt,
|
||||
timm:$ordering),
|
||||
(AMOInst GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt,
|
||||
timm:$ordering)>;
|
||||
|
||||
let Size = 28 in
|
||||
def PseudoMaskedAtomicSwap32 : PseudoMaskedAMO;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_xchg_i32,
|
||||
PseudoMaskedAtomicSwap32>;
|
||||
let Size = 28 in
|
||||
def PseudoMaskedAtomicLoadAdd32 : PseudoMaskedAMO;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_add_i32,
|
||||
PseudoMaskedAtomicLoadAdd32>;
|
||||
let Size = 28 in
|
||||
def PseudoMaskedAtomicLoadSub32 : PseudoMaskedAMO;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_sub_i32,
|
||||
PseudoMaskedAtomicLoadSub32>;
|
||||
let Size = 32 in
|
||||
def PseudoMaskedAtomicLoadNand32 : PseudoMaskedAMO;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_nand_i32,
|
||||
PseudoMaskedAtomicLoadNand32>;
|
||||
let Size = 44 in
|
||||
def PseudoMaskedAtomicLoadMax32 : PseudoMaskedAMOMinMax;
|
||||
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_max_i32,
|
||||
PseudoMaskedAtomicLoadMax32>;
|
||||
let Size = 44 in
|
||||
def PseudoMaskedAtomicLoadMin32 : PseudoMaskedAMOMinMax;
|
||||
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_min_i32,
|
||||
PseudoMaskedAtomicLoadMin32>;
|
||||
let Size = 36 in
|
||||
def PseudoMaskedAtomicLoadUMax32 : PseudoMaskedAMOUMinUMax;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umax_i32,
|
||||
PseudoMaskedAtomicLoadUMax32>;
|
||||
let Size = 36 in
|
||||
def PseudoMaskedAtomicLoadUMin32 : PseudoMaskedAMOUMinUMax;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin_i32,
|
||||
PseudoMaskedAtomicLoadUMin32>;
|
||||
|
||||
/// Compare and exchange
|
||||
|
||||
class PseudoCmpXchg
|
||||
: Pseudo<(outs GPR:$res, GPR:$scratch),
|
||||
(ins GPR:$addr, GPR:$cmpval, GPR:$newval, ixlenimm:$ordering), []> {
|
||||
let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
let hasSideEffects = 0;
|
||||
let Size = 16;
|
||||
}
|
||||
|
||||
// Ordering constants must be kept in sync with the AtomicOrdering enum in
|
||||
// AtomicOrdering.h.
|
||||
multiclass PseudoCmpXchgPat<string Op, Pseudo CmpXchgInst> {
|
||||
def : Pat<(!cast<PatFrag>(Op#"_monotonic") GPR:$addr, GPR:$cmp, GPR:$new),
|
||||
(CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 2)>;
|
||||
def : Pat<(!cast<PatFrag>(Op#"_acquire") GPR:$addr, GPR:$cmp, GPR:$new),
|
||||
(CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 4)>;
|
||||
def : Pat<(!cast<PatFrag>(Op#"_release") GPR:$addr, GPR:$cmp, GPR:$new),
|
||||
(CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 5)>;
|
||||
def : Pat<(!cast<PatFrag>(Op#"_acq_rel") GPR:$addr, GPR:$cmp, GPR:$new),
|
||||
(CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 6)>;
|
||||
def : Pat<(!cast<PatFrag>(Op#"_seq_cst") GPR:$addr, GPR:$cmp, GPR:$new),
|
||||
(CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 7)>;
|
||||
}
|
||||
|
||||
def PseudoCmpXchg32 : PseudoCmpXchg;
|
||||
defm : PseudoCmpXchgPat<"atomic_cmp_swap_32", PseudoCmpXchg32>;
|
||||
|
||||
def PseudoMaskedCmpXchg32
|
||||
: Pseudo<(outs GPR:$res, GPR:$scratch),
|
||||
(ins GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask,
|
||||
ixlenimm:$ordering), []> {
|
||||
let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
let hasSideEffects = 0;
|
||||
let Size = 32;
|
||||
}
|
||||
|
||||
def : Pat<(int_riscv_masked_cmpxchg_i32
|
||||
GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering),
|
||||
(PseudoMaskedCmpXchg32
|
||||
GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering)>;
|
||||
|
||||
} // Predicates = [HasStdExtA]
|
||||
|
||||
let Predicates = [HasStdExtA, IsRV64] in {
|
||||
|
||||
defm : AMOPat<"atomic_swap_64", "AMOSWAP_D">;
|
||||
defm : AMOPat<"atomic_load_add_64", "AMOADD_D">;
|
||||
defm : AMOPat<"atomic_load_and_64", "AMOAND_D">;
|
||||
defm : AMOPat<"atomic_load_or_64", "AMOOR_D">;
|
||||
defm : AMOPat<"atomic_load_xor_64", "AMOXOR_D">;
|
||||
defm : AMOPat<"atomic_load_max_64", "AMOMAX_D">;
|
||||
defm : AMOPat<"atomic_load_min_64", "AMOMIN_D">;
|
||||
defm : AMOPat<"atomic_load_umax_64", "AMOMAXU_D">;
|
||||
defm : AMOPat<"atomic_load_umin_64", "AMOMINU_D">;
|
||||
|
||||
/// 64-bit AMOs
|
||||
|
||||
def : Pat<(i64 (atomic_load_sub_64_monotonic GPR:$addr, GPR:$incr)),
|
||||
(AMOADD_D GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
def : Pat<(i64 (atomic_load_sub_64_acquire GPR:$addr, GPR:$incr)),
|
||||
(AMOADD_D_AQ GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
def : Pat<(i64 (atomic_load_sub_64_release GPR:$addr, GPR:$incr)),
|
||||
(AMOADD_D_RL GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
def : Pat<(i64 (atomic_load_sub_64_acq_rel GPR:$addr, GPR:$incr)),
|
||||
(AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
def : Pat<(i64 (atomic_load_sub_64_seq_cst GPR:$addr, GPR:$incr)),
|
||||
(AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
|
||||
|
||||
/// 64-bit pseudo AMOs
|
||||
|
||||
let Size = 20 in
|
||||
def PseudoAtomicLoadNand64 : PseudoAMO;
|
||||
// Ordering constants must be kept in sync with the AtomicOrdering enum in
|
||||
// AtomicOrdering.h.
|
||||
def : Pat<(i64 (atomic_load_nand_64_monotonic GPR:$addr, GPR:$incr)),
|
||||
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 2)>;
|
||||
def : Pat<(i64 (atomic_load_nand_64_acquire GPR:$addr, GPR:$incr)),
|
||||
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 4)>;
|
||||
def : Pat<(i64 (atomic_load_nand_64_release GPR:$addr, GPR:$incr)),
|
||||
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 5)>;
|
||||
def : Pat<(i64 (atomic_load_nand_64_acq_rel GPR:$addr, GPR:$incr)),
|
||||
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 6)>;
|
||||
def : Pat<(i64 (atomic_load_nand_64_seq_cst GPR:$addr, GPR:$incr)),
|
||||
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 7)>;
|
||||
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_xchg_i64,
|
||||
PseudoMaskedAtomicSwap32>;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_add_i64,
|
||||
PseudoMaskedAtomicLoadAdd32>;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_sub_i64,
|
||||
PseudoMaskedAtomicLoadSub32>;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_nand_i64,
|
||||
PseudoMaskedAtomicLoadNand32>;
|
||||
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_max_i64,
|
||||
PseudoMaskedAtomicLoadMax32>;
|
||||
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_min_i64,
|
||||
PseudoMaskedAtomicLoadMin32>;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umax_i64,
|
||||
PseudoMaskedAtomicLoadUMax32>;
|
||||
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin_i64,
|
||||
PseudoMaskedAtomicLoadUMin32>;
|
||||
|
||||
/// 64-bit compare and exchange
|
||||
|
||||
def PseudoCmpXchg64 : PseudoCmpXchg;
|
||||
defm : PseudoCmpXchgPat<"atomic_cmp_swap_64", PseudoCmpXchg64>;
|
||||
|
||||
def : Pat<(int_riscv_masked_cmpxchg_i64
|
||||
GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering),
|
||||
(PseudoMaskedCmpXchg32
|
||||
GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering)>;
|
||||
} // Predicates = [HasStdExtA, IsRV64]
|
||||
|
|
@ -752,6 +752,27 @@ def : InstAlias<"c.fsdsp $rs2, (${rs1})", (C_FSDSP FPR64C:$rs2, SPMem:$rs1, 0)>;
|
|||
// Compress Instruction tablegen backend.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class SelectCompressOpt<CondCode Cond>: Pat<
|
||||
(riscv_selectcc_frag:$select GPR:$lhs, simm12_no6:$Constant, Cond,
|
||||
GPR:$truev, GPR:$falsev),
|
||||
(Select_GPR_Using_CC_GPR (ADDI GPR:$lhs, (NegImm simm12:$Constant)), X0,
|
||||
(IntCCtoRISCVCC $select), GPR:$truev, GPR:$falsev)>;
|
||||
|
||||
class UniBrccCompressOpt<CondCode Cond, RVInstB Inst> : Pat<
|
||||
(UniformTetradFrag<riscv_brcc> GPR:$lhs, simm12_no6:$Constant, Cond, bb:$place),
|
||||
(Inst (ADDI GPR:$lhs, (NegImm simm12:$Constant)), X0, bb:$place)>;
|
||||
|
||||
def OptForMinSize : Predicate<"MF ? MF->getFunction().hasMinSize() : false">;
|
||||
|
||||
let Predicates = [HasStdExtC, OptForMinSize] in {
|
||||
def : SelectCompressOpt<SETEQ>;
|
||||
def : SelectCompressOpt<SETNE>;
|
||||
|
||||
def : UniBrccCompressOpt<SETEQ, BEQ>;
|
||||
def : UniBrccCompressOpt<SETNE, BNE>;
|
||||
}
|
||||
|
||||
|
||||
// Patterns are defined in the same order the compressed instructions appear
|
||||
// on page 82 of the ISA manual.
|
||||
|
||||
|
|
|
|||
|
|
@ -67,42 +67,42 @@ def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">,
|
|||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let Predicates = [HasStdExtMOrZmmul] in {
|
||||
def : PatGprGpr<mul, MUL>;
|
||||
def : PatGprGpr<mulhs, MULH>;
|
||||
def : PatGprGpr<mulhu, MULHU>;
|
||||
def : PatGprGpr<riscv_mulhsu, MULHSU>;
|
||||
def : PatGprGpr<UniformBinFrag<mul>, MUL>;
|
||||
def : PatGprGpr<UniformBinFrag<mulhs>, MULH>;
|
||||
def : PatGprGpr<UniformBinFrag<mulhu>, MULHU>;
|
||||
def : PatGprGpr<UniformBinFrag<riscv_mulhsu>, MULHSU>;
|
||||
} // Predicates = [HasStdExtMOrZmmul]
|
||||
|
||||
let Predicates = [HasStdExtM] in {
|
||||
def : PatGprGpr<sdiv, DIV>;
|
||||
def : PatGprGpr<udiv, DIVU>;
|
||||
def : PatGprGpr<srem, REM>;
|
||||
def : PatGprGpr<urem, REMU>;
|
||||
def : PatGprGpr<UniformBinFrag<sdiv>, DIV>;
|
||||
def : PatGprGpr<UniformBinFrag<udiv>, DIVU>;
|
||||
def : PatGprGpr<UniformBinFrag<srem>, REM>;
|
||||
def : PatGprGpr<UniformBinFrag<urem>, REMU>;
|
||||
} // Predicates = [HasStdExtM]
|
||||
|
||||
// Select W instructions if only the lower 32-bits of the result are used.
|
||||
let Predicates = [HasStdExtMOrZmmul, IsRV64] in
|
||||
def : PatGprGpr<binop_allwusers<mul>, MULW>;
|
||||
def : PatGprGpr<UniformWBinFrag<mul>, MULW>;
|
||||
|
||||
let Predicates = [HasStdExtM, IsRV64] in {
|
||||
def : PatGprGpr<riscv_divw, DIVW>;
|
||||
def : PatGprGpr<riscv_divuw, DIVUW>;
|
||||
def : PatGprGpr<riscv_remuw, REMUW>;
|
||||
def : PatGprGpr<UniformWBinFrag<riscv_divw>, DIVW>;
|
||||
def : PatGprGpr<UniformWBinFrag<riscv_divuw>, DIVUW>;
|
||||
def : PatGprGpr<UniformWBinFrag<riscv_remuw>, REMUW>;
|
||||
|
||||
// Handle the specific cases where using DIVU/REMU would be correct and result
|
||||
// in fewer instructions than emitting DIVUW/REMUW then zero-extending the
|
||||
// result.
|
||||
def : Pat<(and (riscv_divuw (assertzexti32 GPR:$rs1),
|
||||
(assertzexti32 GPR:$rs2)), 0xffffffff),
|
||||
def : Pat<(UniformBinFrag<and> (riscv_divuw (assertzexti32 GPR:$rs1),
|
||||
(assertzexti32 GPR:$rs2)), 0xffffffff),
|
||||
(DIVU GPR:$rs1, GPR:$rs2)>;
|
||||
def : Pat<(and (riscv_remuw (assertzexti32 GPR:$rs1),
|
||||
(assertzexti32 GPR:$rs2)), 0xffffffff),
|
||||
def : Pat<(UniformBinFrag<and> (riscv_remuw (assertzexti32 GPR:$rs1),
|
||||
(assertzexti32 GPR:$rs2)), 0xffffffff),
|
||||
(REMU GPR:$rs1, GPR:$rs2)>;
|
||||
|
||||
// Although the sexti32 operands may not have originated from an i32 srem,
|
||||
// this pattern is safe as it is impossible for two sign extended inputs to
|
||||
// produce a result where res[63:32]=0 and res[31]=1.
|
||||
def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
|
||||
def : Pat<(UniformBinFrag<srem> (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
|
||||
(REMW GPR:$rs1, GPR:$rs2)>;
|
||||
} // Predicates = [HasStdExtM, IsRV64]
|
||||
|
||||
|
|
@ -111,6 +111,6 @@ let Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba] in {
|
|||
// multiply where the inputs aren't known to be zero extended. We can shift the
|
||||
// inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish
|
||||
// zeroing the upper 32 bits.
|
||||
def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))),
|
||||
def : Pat<(i64 (UniformBinFrag<mul> (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))),
|
||||
(MULHU (SLLI GPR:$rs1, 32), (SLLI GPR:$rs2, 32))>;
|
||||
} // Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba]
|
||||
|
|
|
|||
Loading…
Reference in New Issue