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70115 Commits

Author SHA1 Message Date
zhoujing 967cb725c8 [VENTUS][RISCV][feat] Set ventus kernel for OpenCL kernel functions 2023-06-05 13:10:35 +08:00
zhoujing 8e86eb368c [VENTUS][RISCV][workflow] Modify workflow script 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-31 12:03:02 +08:00
zhoujing 7d66e05b28 [VENTUS][RISCV][fix] Fix insert join instructions pass bug 
After this fix, the vbeq/join instructions codegen are normal now

Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-31 12:02:27 +08:00
zhoujing 8c7f5a3c28 [VENTUS][RISCV][fix] Fix instructuions which contain 5 bits unsigned immediate asmParser && pattern bug 2023-05-26 17:52:36 +08:00
zhoujing b22d7bd36f [VENTUS][RISCV][fix] Fix vlw/vsw instructions' pattern 2023-05-26 11:12:48 +08:00
zhoujing a17f01270b [VENTUS][RISCV][fix] Fix vlw12.v/vsw12.v instructions' codegen pattern 
Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-05-25 14:49:48 +08:00
zhoujingya ad23baaa51 [VENTUS][RISCV][feat] Add more floating point instructions pattern 
Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-05-25 14:48:30 +08:00
zhoujing 5d29133ab0 [VENTUS][RISCV][fix] Add isReturn block check before insertation 2023-05-25 14:09:12 +08:00
zhoujingya c0cdbbc172 [VENTUS][RISCV][style] Formatting && Change function and variable names 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-05-12 17:41:45 +08:00
zhoujingya 961d5a6b42 [VENTUS][RISCV][fix] Uncomment missing assertation 2023-05-12 14:46:27 +08:00
zhoujingya 97a3f99e4c [VENTUS][RISCV][pass] Add insert join instruction pass for VBranch 
we follow the following rules to insert join block and join instruction

 1: Legalize all the return block
    when there are one more return blocks in machine function, there must be
    branches, we need to reduce return blocks number down to 1
 1.1: If two return blocks have common nearest parent branch, this two blocks
    need to be joined, and we add a hasBeenJoined marker for this parent
    branch
 1.2: after we complete 1.1 process, there maybe one more return blocks, we
    need to further add join block, we recursively build dominator tree for
    these return blocks, first we find the nearest common dominator branch for
    two return blocks, and then get dominator tree path between dominator
    and each return block, we need to check this path in which whether any
    other branch blocks exists, ideally, the branch block in path should have
    been joined and marked, if not, this path is illegal, these two block can
    not be joined

 2: Insert join instructions
 2.1: we scan through the MachineBasic blocks and check what blocks to insert
    join instruction, below MBB represents MachineBasic Block
 2.2: The MBB must have one more predecessors and its nearest dominator must
     be a VBranch
 2.3: Then we analyze the the predecessor of MBB, if the predecessor
    has single successor, we add a join instruction to the predecessor end,
    other wise, we need to insert a join block between predecessor and MBB
 2023-05-12 14:01:57 +08:00
zhoujingya 5f776bde21 [VENTUS][RISCV][fix] Constraint divergent private load/store instructions can only use tp register 2023-04-27 09:32:25 +08:00
zhoujingya ea75d078fb [VENTUS][RISCV][feat] Add zfinx support 
Because there is no `F` extension and float registers in ventus, we need to
support `zfinx` to generate common float instructions
 2023-04-23 11:29:09 +08:00
zhoujingya 9d9283fa7b [VENTUS][RISCV][fix] Fix ventus abi and calling convention 
Kernel functions use sp as GPRs spill stack slots
Non-kernel functions use tp as VGPRs spill stack slots
 2023-04-20 15:27:52 +08:00
zhoujingya f28e6c5e38 [VENTUS][RISCV][feat] Add vararg backend support in ventus 
We adjust the stack growing direction early months for OpenCL, in order to be
compatible with current architecture, we need to do some modification to
support vararg
 2023-04-18 10:03:53 +08:00
zhoujingya b01963690d [VENTUS][RISCV][fix] Fix vsw/vlw encoding bugs and update test cases 
Fix vlw/vsw instructions' encoding since them have been updated
 2023-04-17 18:07:33 +08:00
zhoujingya 8ba248d102 [VENTUS][RISCV] Add vararg support 
Because ventus riscv is designed specially for OpenCL language, we originally add or remove some language features mainly for serving OpenCL, but we now need to add customized `printf` function which is expected to be written in C, so we need also to add support for C language features in current ventus

Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-04-13 15:00:35 +08:00
zhoujingya 458808b5d1 Remove FeatureStdExtC in ventus 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-03-30 10:14:52 +08:00
zhoujingya 625746818d Fix vlw12/vsw12 assembly code generation bugs * Before: vsw12.v v1, zero(v0) * After: vsw12.v v1, 0(v0) 
Signed-off-by: zhoujingya <jing.zhou@terapines.com>
 2023-03-28 13:49:47 +08:00
zhoujingya 2b54041ac3 Fix encoding bug for endprg&vmx.v.x&barrier 2023-03-27 17:44:38 +08:00
zhoujingya 6f45d90f90 Update vlw12/vsw12 instructions' encoding 2023-03-23 17:21:38 +08:00
zhoujingya 94597a71ad Fix the encoding bug of barrier 2023-03-22 17:55:22 +08:00
zhoujingya 53c8b524e8 Add vsetvli instruction to support spike 2023-03-21 15:48:54 +08:00
zhoujingya dfc6b4d7f0 Fix VI instruction codegen bug && disable declare-opencl-builtins option for opencl 2023-03-20 16:30:08 +08:00
zhoujingya 553e65dcf7 Change barrier and work_group_barrier into builtin functions 2023-03-14 10:38:22 +08:00
zhoujingya ad550a1375 Update load/store instructions pattern && add test cases for load/store codegen 2023-03-03 11:41:13 +08:00
zhoujing ff4e666b80 Fix addrRegReg bug & Add pattern for load/store 
* TODO: Need to write test files later
 2023-02-28 22:04:07 +08:00
zhoujing 60a504f481 Update customized instructions' encoding 2023-02-24 11:21:19 +08:00
zhoujing a92723f212 Update barrier intrinsics' name and modify barrier's encoding 2023-02-10 14:50:40 +08:00
zhoujing 23fe611d6e Fix barriersub instruction pattern match bug 2023-02-10 10:44:22 +08:00
zhoujing 18810a86c0 Update barrier&barriersub instructions, codegen test cases for barrier builtins and intrinsics 2023-02-10 10:27:46 +08:00
zhoujing f75aab9a57 Fix endprg's encoding and add barrier instruction 2023-02-08 11:35:57 +08:00
zhoujing 47fc50bb92 Add pass to support VX/VF instruction generation 
Summary: Add pass to support VX/VF instruction generation

Test Plan: none

Reviewers: hualin

Reviewed By: hualin

Subscribers: yanming

Differential Revision: http://www.tpt.com/D583
 2023-02-07 14:00:15 +08:00
zhoujing e74aafb0d6 Change vftta&vfexp instructions' encoding formats 2023-01-28 10:46:31 +08:00
Aries 9318d5354f [NFC] Fix coding style 2023-01-28 09:53:19 +08:00
Aries 192ee0187a [NFC] Fix coding style 2023-01-28 09:49:39 +08:00
zhoujing 93143b5b35 Add definition for vfexp/vftta 2023-01-20 09:57:19 +08:00
Aries 438f1c92c4 Fix some build warnings 2023-01-19 09:45:27 +08:00
Aries 890dddc205 Add missing C ext feature to Ventus GPGPU 2023-01-18 15:09:38 +08:00
Aries 71979c7b0d [NFC] Add comment to FLW/FSW 2023-01-18 15:09:18 +08:00
zhoujing eecbe33eb1 Fix instruction encoding conflicts 2023-01-18 11:20:14 +08:00
zhoujing 229b27b714 Update instructions for vector load/store 2023-01-17 17:46:59 +08:00
Aries 2c6aaa910c Add endprg, vid.v instruction definition 2023-01-17 14:39:57 +08:00
zhoujing 23821f9116 Change some patterns' format 2023-01-17 09:34:59 +08:00
Aries 2d601dc47f Fix bug for Ventus TTI getRegisterBitWidth 2023-01-16 16:06:53 +08:00
Aries f933867e85 Fix linking error with pocl when llvm is built as shared libraries 2023-01-16 16:03:17 +08:00
zhoujing a81a56274f Update float point instructions test case 2023-01-12 16:43:47 +08:00
zhoujing fcd285daae Modify file formats && add predicate for float point instruction 
* Based on zcc commit: 6e63555df68b5ce96d0af3dceb822abb2a2c9481
 2023-01-10 10:25:58 +08:00
zhoujing 7e701d4ba1 Add support for float point trunc instruction match 2023-01-09 18:06:39 +08:00
zhoujing 899ca9fd8e Add support for 12 bits immediate 2023-01-09 11:59:45 +08:00