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444583 Commits

Author SHA1 Message Date
Jules-Kong 6b6111168a [Ventus][Feature] Add csrr vector version 2024-11-08 01:30:06 +08:00
Jules-Kong 5032490e31 [Ventus][Work-item] Optimize Work-item built-in functions 2024-11-07 17:24:23 +08:00
Jules-Kong 0f31d6ca08
Merge pull request #148 from xlinsist/prepare-setup 
[VENTUS][README] Add pocl example and improve readability.
 2024-09-30 13:30:56 +08:00
xlinsist cc10cbb44c [VENTUS][README] Add pocl example and improve readability. 2024-09-30 01:04:47 +00:00
ZhouJing(周晶) 0a82f17b0c
Merge pull request #146 from ziliangzl/double-operation 
[Ventus][fix] Fix flw/fsw instruction codegen pattern
 2024-08-21 08:58:11 +08:00
ziliangzl f89036bf68 [Ventus][fix] Fix flw/fsw related codegen test 2024-08-20 10:57:06 +08:00
ziliangzl 84b7c666eb [Ventus][fix] Fix flw/fsw instruction pattern 2024-08-20 09:59:25 +08:00
ZhouJing(周晶) 593cad12fc
Merge pull request #144 from THU-DSP-LAB/update-workflow 
[ventus][NFC] Update workflow script
 2024-08-16 08:54:35 +08:00
Jules-Kong 030ea4fc53 [ventus][NFC] Update workflow script 2024-08-15 20:18:24 +08:00
wangqinfan 64ebe150c6
Merge pull request #143 from THU-DSP-LAB/fix-something 
[ventus][NFC] Fix something wrong
 2024-08-15 14:32:59 +08:00
Jules-Kong 058a3d891d [ventus][NFC] Replace the rodinia's code repository 2024-08-15 10:56:07 +08:00
Jules-Kong 4a6b4f5460 [VENTUS][NFC] 1k for each warp 
Ventus sets the 1k size for a single warp.
 2024-08-14 18:08:27 +08:00
Jules-Kong 01a9dcb5b6 [VENTUS][NFC] Fix some unreasonable places 2024-08-14 17:23:50 +08:00
ZhouJing(周晶) 6c682d4d14
Merge pull request #142 from THU-DSP-LAB/fix_centos_dockerfile 
[ventus][fix] Fix the dockerfile file of centos
 2024-08-14 15:40:31 +08:00
Jules-Kong 3e46bca67d [ventus][fix] Fix the dockerfile file of centos 
1. Change the registry mirror.
2. Use the system default compiler.
 2024-08-14 15:27:28 +08:00
ZhouJing(周晶) c9f7a7767b
Merge pull request #141 from ziliangzl/double-operation 
[Ventus][fix] Fix #140 complete double type support for smoothstep function
 2024-08-13 17:50:58 +08:00
ziliangzl 8328c0d01d [Ventus][fix] Fix #140 complete double type support of smoothstep function 2024-08-13 17:35:20 +08:00
ZhouJing(周晶) 18566fcdd2
Merge pull request #139 from ziliangzl/double-operation 
[VENTUS][fix] Fix double add and mul operation
 2024-08-07 13:40:26 +08:00
ZiliangZhang 2f528a1c7b
Merge branch 'main' into double-operation 2024-07-24 10:50:04 +08:00
ziliangzl 5b1f7d5875 [VENTUS][fix]Fix double add and mul operation 
Passed test_geometrics in CTS.
 2024-07-24 10:32:18 +08:00
Jules-Kong 51b7f8d11e
Merge pull request #137 from summersurface/main 
[Dockerfile] Add ubuntu 22.04 dockerfile
 2024-07-09 00:48:16 +08:00
马钿雨 5ebf18d031
Add files via upload 2024-07-08 19:13:59 +08:00
ZiliangZhang d704c61892
Merge pull request #133 from ziliangzl/shuffle 
[Ventus][fix]Fix libclc shuffle function
 2024-06-27 16:41:39 +08:00
ziliangzl 09b59af05a [Ventus][fix]Fix libclc shuffle function 
Passed OPENCL-CTS shuffle_built_in testcase
 2024-06-27 16:25:24 +08:00
wangqinfan ecddf383ed
Merge pull request #132 from THU-DSP-LAB/add-some-configuration 
[VENTUS][Configuration] Add some configuration
 2024-06-26 15:15:52 +08:00
Jules-Kong 3581f12d5e [VENTUS][Configuration] Add some configuration 
1. Add the dockerfile file of centos;
2. Set codeowners;
 2024-06-26 13:43:38 +08:00
zhoujingya ddc7052d4a
Merge pull request #130 from THU-DSP-LAB/memory 
[VENTUS][fix] Fix memory flags set in tablegen #129
 2024-06-25 16:46:33 +08:00
zhoujingya aeee8ee171 [VENTUS][fix] Fix memory flags set in tablegen #129 
In previous logic ,default memory access flag is 0b00, this will cause
all no-local/no-private related instructions return true when fall into
`RISCVInstrInfo::isUniformMemoryAccess` logic
 2024-06-24 23:01:47 +08:00
zhoujingya a320670f44
Merge pull request #128 from THU-DSP-LAB/memory 
[VENTUS][fix] Add memory access flags in tablegen
 2024-06-14 17:22:26 +08:00
zhoujing 625facb350 [VENTUS][fix] Add memory access flags in tablegen 
In this way, it is better to judge what memory scope is accessed by
load/store instructions
 2024-06-14 09:46:00 +08:00
ZiliangZhang c955d0a29c
Merge pull request #127 from ziliangzl/local-mem 
[Ventus][fix]Fix missing vmv instruction for FrameReg in divergent path
 2024-06-07 09:38:55 +08:00
ziliangzl 0b03e6b411 [Ventus][fix]Fix missing vmv instruction for FrameReg in divergent path 2024-06-06 16:16:57 +08:00
zhoujingya 3fffdc5d16
Merge pull request #115 from THU-DSP-LAB/workitem 
[VENTUS][fix] Add function sections for workitem functions to reduce binary size
 2024-06-04 08:56:25 +08:00
zhoujingya 492b35de44
Merge pull request #126 from THU-DSP-LAB/readme 
[NFC][readme] Modify some compiler flags
 2024-06-03 16:48:18 +08:00
zhoujing 3abe6bd242 [NFC][readme] Modify some compiler flags 2024-06-03 16:47:28 +08:00
zhoujing bdfa4ec6af [VENTUS][fix] Add function sections for workitem functions 
Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2024-05-31 22:29:05 +08:00
zhoujingya 7c78b29815
Merge pull request #122 from THU-DSP-LAB/compress_instruction_disassemble 
[VENTUS][fix] Disable compress instruction disassemble
 2024-05-30 14:38:50 +08:00
ZiliangZhang 76ed2fc9e3
Merge pull request #121 from ziliangzl/vmsle 
[VENTUS][fix] Fix missing regexti instruction for vmsle instruction
 2024-05-23 09:06:58 +08:00
ziliangzl 11b55acb48 [VENTUS][fix]Fix missing regext instruction for vmsle instruction 
This bug caused PseudoVMSLT_VI node didn't insert regext.
Now OPENCL-CTS relationals test passed.
 2024-05-21 17:09:48 +08:00
zhoujingya 9d966660b6
Merge pull request #116 from ziliangzl/inline-asm 
[VENTUS][NFC] Add inline assembly codes testcase
 2024-05-20 09:43:55 +08:00
zhoujingya c168c442ce
Merge pull request #118 from THU-DSP-LAB/checkInstr 
[VENTUS][fix] Assign initial value for VastartStoreFrameIndex
 2024-05-18 14:17:34 +08:00
ziliangzl 60f388930d [VENTUS][fix]Assign initial value for VastartStoreFrameIndex 
VastartStoreFrameIndex havn't initial value, caused issue THU-DSP-LAB/llvm-project#117
 2024-05-15 13:39:07 +08:00
ziliangzl 451062314a
Merge pull request #119 from ziliangzl/workgroup 
[VENTUS][libclc][feat] Add missing workgroup function implementations
 2024-05-15 11:36:10 +08:00
qinfan b465e58817 [VENTUS][fix] Add a switch to the C extension 
Add a switch to the C extension, now the C extension is turned off by default.
 2024-05-14 17:26:24 +08:00
ziliangzl 6a8e4d4667 [VENTUS][#119]Fix workgroup function barrier scope 2024-05-14 14:03:20 +08:00
ziliangzl d977b0bf8b [VENTUS][#119]Complete workgroup function implementation 
Implement work_group_reduce_<op> functions in wgreduce.cl .
Implement work_group_scan_inclusive_<op> work_group_scan_exclusive_<op> functions in wgscan.cl .
Passed corresponding OPENCL-CTS tests.
 2024-05-14 13:36:09 +08:00
qinfan 408ed74df2 [VENTUS][fix] Modify the disassembly result of a compress instruction error 
Modify the disassembly result of a compress instruction error.
 2024-05-13 15:57:55 +08:00
ziliangzl 4789f2096b [VENTUS][#119]Add work_group_broadcast implementation 
Passed corresponding OPENCL-CTS test.
 2024-05-13 11:22:56 +08:00
ziliangzl d63caa094a [VENTUS][#119]Fix __wg_scratch multiple define 
1.Global variable shouldn't define in header.
2.Fix code format.
 2024-05-13 11:18:03 +08:00
ziliangzl 6b70120436 [VENTUS][libclc][feat]Start workgroup function implementation 
1.Implement barrier and work_group_barrier function with intrinsics.
2.Implement work_group_all and work_group_any function,passed corresponding OPENCL-CTS test.
 2024-05-11 16:38:52 +08:00