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[Ventus][Feature] Add csrr vector version

This commit is contained in:
Jules-Kong 2024-11-08 00:54:59 +08:00
parent 5032490e31
commit 6b6111168a
2 changed files with 27 additions and 0 deletions
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17
llvm/lib/Target/RISCV/RISCVInstrFormats.td
View File

@ -148,6 +148,7 @@ def OPC_CUSTOM_4 : RISCVOpcode<"CUSTOM_4", 0b1011111>;
def OPC_BRANCH : RISCVOpcode<"BRANCH", 0b1100011>;
def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>;
def OPC_JAL : RISCVOpcode<"JAL", 0b1101111>;
def OPC_SYSTEM_V : RISCVOpcode<"SYSTEM_V", 0b1110010>;
def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>;
def OPC_CUSTOM_3 : RISCVOpcode<"CUSTOM_3", 0b1111011>;
@ -376,6 +377,22 @@ class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
let CustomConstraints = "$rd = 0,$rs1 = 1";
}
class RVInstIV<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
bits<12> imm12;
bits<5> rs1;
bits<5> vd;
let Inst{31-20} = imm12;
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = vd;
let Opcode = opcode.Value;
let CustomConstraints = "$vd = 0,$rs1 = 1";
}
class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {

10
llvm/lib/Target/RISCV/VentusInstrInfo.td
View File

@ -775,6 +775,12 @@ class CSR_ir<bits<3> funct3, string opcodestr>
: RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>;
let hasNoSchedulingInfo = 1,
hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
class CSR_ir_v<bits<3> funct3, string opcodestr>
: RVInstIV<funct3, OPC_SYSTEM_V, (outs VGPR:$vd), (ins csr_sysreg:$imm12, GPR:$rs1),
opcodestr, "$vd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>;
let hasNoSchedulingInfo = 1,
hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
class CSR_ii<bits<3> funct3, string opcodestr>
@ -965,6 +971,8 @@ def CSRRWI : CSR_ii<0b101, "csrrwi">;
def CSRRSI : CSR_ii<0b110, "csrrsi">;
def CSRRCI : CSR_ii<0b111, "csrrci">;
def CSRRSV : CSR_ir_v<0b010, "csrrs.v">;
/// RV64I instructions
let Predicates = [IsRV64] in {
@ -1269,6 +1277,8 @@ def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>;
def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>;
def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>;
def : InstAlias<"csrr.v $vd, $csr", (CSRRSV VGPR:$vd, csr_sysreg:$csr, X0)>;
let EmitPriority = 0 in {
def : InstAlias<"csrw $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>;
def : InstAlias<"csrs $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>;