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Merge pull request #146 from ziliangzl/double-operation 

[Ventus][fix] Fix flw/fsw instruction codegen pattern
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ZhouJing(周晶) 2024-08-21 08:58:11 +08:00 committed by GitHub
parent 593cad12fc f89036bf68
commit 0a82f17b0c
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2 changed files with 9 additions and 8 deletions
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11
llvm/lib/Target/RISCV/VentusInstrInfoF.td
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@ -656,13 +656,14 @@ defm Select_FPR32 : SelectCC_GPR_rrirr<GPRF32>;
def PseudoVFROUND_S : PseudoVFROUND<VGPR>;
def PseudoFROUND_S : PseudoFROUND<GPRF32>;
// /// Loads
/// Loads
defm : UniformLdPat<load, PseudoFLW, f32>;
def : Pat<(f32 (load (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
(COPY_TO_REGCLASS (LW GPR:$rs1, simm12:$imm12), GPRF32)>;
// /// Stores
defm : UniformStPat<store, PseudoFSW, GPRF32, f32>;
/// Stores
def : Pat<(store (f32 FPR32INX:$rs2), (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),
(SW (COPY_TO_REGCLASS FPR32INX:$rs2, GPR), GPR:$rs1, simm12:$imm12)>;
} // Predicates = [HasStdExtZfinx]

6
llvm/test/CodeGen/RISCV/VentusGPGPU/kernel_args.ll
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@ -29,12 +29,12 @@ define dso_local ventus_kernel void @float_add(ptr addrspace(1) nocapture nounde
; VENTUS-LABEL: float_add:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lw t0, 4(a0)
; VENTUS-NEXT: flw t0, 0(t0)
; VENTUS-NEXT: lw t0, 0(t0)
; VENTUS-NEXT: lui t1, %hi(.LCPI1_0)
; VENTUS-NEXT: flw t1, %lo(.LCPI1_0)(t1)
; VENTUS-NEXT: lw t1, %lo(.LCPI1_0)(t1)
; VENTUS-NEXT: fadd.s t0, t0, t1
; VENTUS-NEXT: lw t1, 0(a0)
; VENTUS-NEXT: fsw t0, 0(t1)
; VENTUS-NEXT: sw t0, 0(t1)
; VENTUS-OBJ: lw t1, 0(t1)
; VENTUS-OBJ: fadd.s t0, t0, t1
; VENTUS-NEXT: ret