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llvm-project/llvm/lib/Target/RISCV
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Aries e6b7935c89 [Ventus] ABI and stack adjustment. 
Remove all SGPRs(except ra) from callee saved register set, as they are mainly used in kernel function.
Unify the stack to use TP only, we will emit customized instructions for SP use which should not be
considered as stack according to LLVM codegen infrastructure(only 1 stack is allowed).
By unifying the stack to TP based, it is much easiler for the backend codegen.
 		2023-06-21 13:08:02 +08:00
..
AsmParser [VENTUS][RISCV][workflow] Modify workflow script 2023-05-31 12:03:02 +08:00
Disassembler [VENTUS][RISCV][fix] Constraint divergent private load/store instructions can only use tp register 2023-04-27 09:32:25 +08:00
GISel [RISCV] Move GlobalISEL specific files to sub-directory [nfc] 2022-11-15 14:24:50 -08:00
MCTargetDesc Fix vlw12/vsw12 assembly code generation bugs * Before: vsw12.v v1, zero(v0) * After: vsw12.v v1, 0(v0) 2023-03-28 13:49:47 +08:00
TargetInfo [RISCV] Re-enable JIT support 2022-08-11 11:41:02 +02:00
CMakeLists.txt [VENTUS][RISCV][pass] Add insert join instruction pass for VBranch 2023-05-12 14:01:57 +08:00
RISCV.h [VENTUS][RISCV][feat] Add VGPRSpill stack id for ventus 2023-06-07 11:57:20 +08:00
RISCV.td Remove FeatureStdExtC in ventus 2023-03-30 10:14:52 +08:00
RISCVAsmPrinter.cpp [VENTUS][RISCV] Add vararg support 2023-04-13 15:00:35 +08:00
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp [RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool. 2022-08-12 22:21:05 -07:00
RISCVExpandAtomicPseudoInsts.cpp [RISCV] Avoid redundant branch-to-branch when expanding cmpxchg 2022-08-17 13:49:15 +01:00
RISCVExpandPseudoInsts.cpp [VENTUS][RISCV][fix] Fix build warning 2023-06-16 10:25:02 +08:00
RISCVFrameLowering.cpp [Ventus] ABI and stack adjustment. 2023-06-21 13:08:02 +08:00
RISCVFrameLowering.h [Ventus] ABI and stack adjustment. 2023-06-21 13:08:02 +08:00
RISCVISelDAGToDAG.cpp [VENTUS][RISCV][fix] Add initial Tp stack size calculation 2023-06-11 12:18:39 +08:00
RISCVISelDAGToDAG.h [VENTUS][RISCV][fix] Add initial Tp stack size calculation 2023-06-11 12:18:39 +08:00
RISCVISelLowering.cpp [VENTUS][RISCV][fix] Add missing flags for building libclc 2023-06-21 10:59:48 +08:00
RISCVISelLowering.h Merge libclc-vector-support 2023-06-16 09:41:08 +08:00
RISCVInstrFormats.td Fix vlw12/vsw12 assembly code generation bugs * Before: vsw12.v v1, zero(v0) * After: vsw12.v v1, 0(v0) 2023-03-28 13:49:47 +08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td [RISCV] Replace hardcoded constant with OPIVI.Value in tablegen. NFC 2022-11-30 20:58:40 -08:00
RISCVInstrInfo.cpp [VENTUS][RISCV][fix] Fix building libclc errors 2023-06-16 17:42:22 +08:00
RISCVInstrInfo.h Add initial support to lower ISD::SELECT into branch instructions in divergent execution path. 2022-12-22 17:17:02 +08:00
RISCVInstrInfo.td [VENTUS][RISCV][fix] Constraint divergent private load/store instructions can only use tp register 2023-04-27 09:32:25 +08:00
RISCVInstrInfoA.td [RISCV] Add target feature to force-enable atomics 2022-08-09 16:04:46 +02:00
RISCVInstrInfoC.td Add MC support of RISCV Zcd Extension 2022-11-24 05:48:06 +08:00
RISCVInstrInfoD.td Propagate uniform execution predicates to all Ventus sALU operations. 2022-12-16 14:04:55 +08:00
RISCVInstrInfoF.td Update customized instructions' encoding 2023-02-24 11:21:19 +08:00
RISCVInstrInfoM.td [RISCV][Clang] Add support for Zmmul extension 2022-07-18 20:26:08 -04:00
RISCVInstrInfoV.td [RISCV][Codegen] Account for LMUL in Vector floating-point instructions 2022-11-30 11:09:21 -08:00
RISCVInstrInfoVPseudos.td [RISCV][Codegen] Account for LMUL in Vector floating-point instructions 2022-11-30 11:09:21 -08:00
RISCVInstrInfoVSDPatterns.td [RISCV] Use _TIED form of VFWADD(U)_WV/VFWSUB(U)_WV to avoid early clobber. 2022-10-03 21:44:08 -07:00
RISCVInstrInfoVVLPatterns.td [VP][RISCV] Add vp.nearbyint and RISC-V support. 2022-11-16 14:05:35 +08:00
RISCVInstrInfoXVentana.td [RISCV] Implement assembler support for XVentanaCondOps 2022-11-14 09:01:54 -08:00
RISCVInstrInfoZb.td Propagate uniform execution predicates to all Ventus sALU operations. 2022-12-16 14:04:55 +08:00
RISCVInstrInfoZfh.td Propagate uniform execution predicates to all Ventus sALU operations. 2022-12-16 14:04:55 +08:00
RISCVInstrInfoZicbo.td [RISCV][NFC] Fix typo in comment in RISCVInstrInfoZicbo.td 2022-09-01 13:49:55 +01:00
RISCVInstrInfoZk.td
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RISCVMCInstLower.cpp Very very early step to remove RVV features from code base. 2022-12-16 17:33:54 +08:00
RISCVMachineFunctionInfo.cpp Update Ventus GPGPU ABI: X4 as stack pointer, V0-V31 as arguments registers etc 2022-12-28 13:11:22 +08:00
RISCVMachineFunctionInfo.h [VENTUS][RISCV][fix] Modify calling convention 2023-06-05 17:11:25 +08:00
RISCVMacroFusion.cpp [RISCV] Be more strict about LUI+ADDI macrofusion pre-RA. 2022-08-21 10:58:15 -07:00
RISCVMacroFusion.h [RISCV] Add macrofusion infrastructure and one example usage. 2022-06-23 08:38:39 -07:00
RISCVMakeCompressible.cpp Define callee saved registers for Ventus GPGPU. 2022-12-28 16:37:38 +08:00
RISCVMergeBaseOffset.cpp [RISCV] Use std::optional in RISCVMergeBaseOffset.cpp (NFC) 2022-11-25 23:08:26 -08:00
RISCVRedundantCopyElimination.cpp [RISCV] Use analyzeBranch in RISCVRedundantCopyElimination. 2022-08-29 09:05:53 -07:00
RISCVRegisterInfo.cpp [Ventus] ABI and stack adjustment. 2023-06-21 13:08:02 +08:00
RISCVRegisterInfo.h Drafting divergent related code, not working yet. 2022-12-19 18:11:34 +08:00
RISCVRegisterInfo.td [RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI 2022-08-24 14:16:20 +00:00
RISCVSExtWRemoval.cpp [RISCV] Remove SExtWRemovalCands set from RISCVSExtWRemoval. 2022-11-21 19:24:02 -08:00
RISCVSchedRocket.td [RISCV] Merge WriteLDW and WriteLDWU schedule classes. 2022-10-28 11:57:33 -07:00
RISCVSchedSiFive7.td [RISCV] Merge WriteLDW and WriteLDWU schedule classes. 2022-10-28 11:57:33 -07:00
RISCVSchedule.td [RISCV] Merge WriteLDW and WriteLDWU schedule classes. 2022-10-28 11:57:33 -07:00
RISCVScheduleV.td [RISCV][Codegen] Account for LMUL in Vector floating-point instructions 2022-11-30 11:09:21 -08:00
RISCVScheduleZb.td [RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC 2022-09-23 21:38:42 -07:00
RISCVSearchableTables.td Drafting divergent related code, not working yet. 2022-12-19 18:11:34 +08:00
RISCVSubtarget.cpp Very very early step to remove RVV features from code base. 2022-12-16 17:33:54 +08:00
RISCVSubtarget.h Change barrier and work_group_barrier into builtin functions 2023-03-14 10:38:22 +08:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp [VENTUS][RISCV][pass] Add insert join instruction pass for VBranch 2023-05-12 14:01:57 +08:00
RISCVTargetMachine.h Add OpenCL addressing space mapping to RISCVAS. 2022-12-20 17:08:08 +08:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp [Ventus] ABI and stack adjustment. 2023-06-21 13:08:02 +08:00
RISCVTargetTransformInfo.h [VENTUS][RISCV][fix] Add more divergence ananlysis 2023-06-15 22:34:40 +08:00
VentusCallingConv.td [Ventus] ABI and stack adjustment. 2023-06-21 13:08:02 +08:00
VentusInsertJoinToVBranch.cpp [VENTUS][RISCV][fix] Fix build warning 2023-06-16 10:25:02 +08:00
VentusInstrFormatsV.td [Ventus] Fix design bug, redesign vlw.v/vsw.v to use vGPR as base address instead of using sGPR. 2023-06-19 12:59:43 +08:00
VentusInstrInfo.td [VENTUS][RISCV][fix] Fix divergent analysis bug for store node 2023-06-12 14:50:55 +08:00
VentusInstrInfoA.td Propagate uniform execution predicates to all Ventus sALU operations. 2022-12-16 14:04:55 +08:00
VentusInstrInfoC.td [VENTUS][RISCV][feat] Add zfinx support 2023-04-23 11:29:09 +08:00
VentusInstrInfoF.td Merge libclc-vector-support 2023-06-16 09:41:08 +08:00
VentusInstrInfoM.td Propagate uniform execution predicates to all Ventus sALU operations. 2022-12-16 14:04:55 +08:00
VentusInstrInfoV.td [VENTUS][RISCV][fix] Fix vsetvli instruction's encoding 2023-06-21 10:16:03 +08:00
VentusInstrInfoVPseudos.td Very very early step to remove RVV features from code base. 2022-12-16 17:33:54 +08:00
VentusInstrInfoVSDPatterns.td Copy RVV codegen pattern related file RISCVInstrInfo*.td to VentusInstrInfo*.td. 2022-12-15 17:04:09 +08:00
VentusInstrInfoVVLPatterns.td Copy RVV codegen pattern related file RISCVInstrInfo*.td to VentusInstrInfo*.td. 2022-12-15 17:04:09 +08:00
VentusRegextInsertion.cpp Add 'regext' instruction definition and insertion pass. 2022-12-29 16:53:18 +08:00
VentusRegisterInfo.td [Ventus] ABI and stack adjustment. 2023-06-21 13:08:02 +08:00
VentusVVInstrConversion.cpp Add pass to support VX/VF instruction generation 2023-02-07 14:00:15 +08:00