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[RISCV] Remove SExtWRemovalCands set from RISCVSExtWRemoval. 

After D137970, we do the fixable instruction conversion in place
so we don't need to worry about iterator invalidation. This lets
us to conversion and updates in a single loop.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D138043
This commit is contained in:
Craig Topper 2022-11-21 19:23:08 -08:00
parent 4e6adb394e
commit f99514ac3a
1 changed files with 30 additions and 37 deletions
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67
llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
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@ -497,10 +497,8 @@ bool RISCVSExtWRemoval::runOnMachineFunction(MachineFunction &MF) {
if (!ST.is64Bit())
return false;
SmallPtrSet<MachineInstr *, 4> SExtWRemovalCands;
bool MadeChange = false;
// Replacing instructions invalidates the MI iterator
// we collect the candidates, then iterate over them separately.
for (MachineBasicBlock &MBB : MF) {
for (auto I = MBB.begin(), IE = MBB.end(); I != IE;) {
MachineInstr *MI = &*I++;
@ -514,42 +512,37 @@ bool RISCVSExtWRemoval::runOnMachineFunction(MachineFunction &MF) {
if (!SrcReg.isVirtual())
continue;
SExtWRemovalCands.insert(MI);
SmallPtrSet<MachineInstr *, 4> FixableDef;
MachineInstr &SrcMI = *MRI.getVRegDef(SrcReg);
// If all definitions reaching MI sign-extend their output,
// then sext.w is redundant
if (!isSignExtendedW(SrcMI, MRI, FixableDef))
continue;
Register DstReg = MI->getOperand(0).getReg();
if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
continue;
// Convert Fixable instructions to their W versions.
for (MachineInstr *Fixable : FixableDef) {
LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
Fixable->setDesc(TII.get(getWOp(Fixable->getOpcode())));
Fixable->clearFlag(MachineInstr::MIFlag::NoSWrap);
Fixable->clearFlag(MachineInstr::MIFlag::NoUWrap);
Fixable->clearFlag(MachineInstr::MIFlag::IsExact);
LLVM_DEBUG(dbgs() << " with " << *Fixable);
++NumTransformedToWInstrs;
}
LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
MRI.replaceRegWith(DstReg, SrcReg);
MRI.clearKillFlags(SrcReg);
MI->eraseFromParent();
++NumRemovedSExtW;
MadeChange = true;
}
}
bool MadeChange = false;
for (auto *MI : SExtWRemovalCands) {
SmallPtrSet<MachineInstr *, 4> FixableDef;
Register SrcReg = MI->getOperand(1).getReg();
MachineInstr &SrcMI = *MRI.getVRegDef(SrcReg);
// If all definitions reaching MI sign-extend their output,
// then sext.w is redundant
if (!isSignExtendedW(SrcMI, MRI, FixableDef))
continue;
Register DstReg = MI->getOperand(0).getReg();
if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
continue;
// Convert Fixable instructions to their W versions.
for (MachineInstr *Fixable : FixableDef) {
LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
Fixable->setDesc(TII.get(getWOp(Fixable->getOpcode())));
Fixable->clearFlag(MachineInstr::MIFlag::NoSWrap);
Fixable->clearFlag(MachineInstr::MIFlag::NoUWrap);
Fixable->clearFlag(MachineInstr::MIFlag::IsExact);
LLVM_DEBUG(dbgs() << " with " << *Fixable);
++NumTransformedToWInstrs;
}
LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
MRI.replaceRegWith(DstReg, SrcReg);
MRI.clearKillFlags(SrcReg);
MI->eraseFromParent();
++NumRemovedSExtW;
MadeChange = true;
}
return MadeChange;
}