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llvm-project/llvm/lib/Target/RISCV
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zhoujingya aeee8ee171 [VENTUS][fix] Fix memory flags set in tablegen #129 
In previous logic ,default memory access flag is 0b00, this will cause
all no-local/no-private related instructions return true when fall into
`RISCVInstrInfo::isUniformMemoryAccess` logic
 		2024-06-24 23:01:47 +08:00
..
AsmParser [VENTUS][fix] Remove instructions not supported by hardware 2023-11-24 17:26:50 +08:00
Disassembler [VENTUS][fix] Add a switch to the C extension 2024-05-14 17:26:24 +08:00
GISel [RISCV] Move GlobalISEL specific files to sub-directory [nfc] 2022-11-15 14:24:50 -08:00
MCTargetDesc [VENTUS][fix] Fix memory flags set in tablegen #129 2024-06-24 23:01:47 +08:00
TargetInfo [RISCV] Re-enable JIT support 2022-08-11 11:41:02 +02:00
CMakeLists.txt [VENTUS][fix] Legalize vlw12.v instruction for variadic functions 2023-09-07 16:39:11 +08:00
RISCV.h [VENTUS][fix] Put local variables declared in kernel function into shared memory 2024-03-05 16:32:59 +08:00
RISCV.td Remove FeatureStdExtC in ventus 2023-03-30 10:14:52 +08:00
RISCVAsmPrinter.cpp Merge pull request #70 from THU-DSP-LAB/resource_manage 2024-02-01 13:17:45 +08:00
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp [RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool. 2022-08-12 22:21:05 -07:00
RISCVExpandAtomicPseudoInsts.cpp [VENTUS][fix] Comment out illegal fmv.w.x instruction and change vmv instructions' format 2023-10-09 14:04:55 +08:00
RISCVExpandPseudoInsts.cpp [VENTUS][fix] Fix register extension 2024-01-23 09:59:51 +08:00
RISCVFrameLowering.cpp [VENTUS][fix] Put local variables declared in kernel function into shared memory 2024-03-05 16:32:59 +08:00
RISCVFrameLowering.h [patch] Add a fix patch from terapines_dev branch 2024-03-08 18:23:47 +08:00
RISCVISelDAGToDAG.cpp [patch] Add a fix patch from terapines_dev branch 2024-03-08 18:23:47 +08:00
RISCVISelDAGToDAG.h [VENTUS][RISCV] Fix VBranch instruction info and select codegen patterns. 2023-06-27 11:12:37 +08:00
RISCVISelLowering.cpp [VENTUS][fix]Fix kernel divergent analysis 2024-04-22 15:53:36 +08:00
RISCVISelLowering.h [VENTUS][fix]Assign initial value for VastartStoreFrameIndex 2024-05-15 13:39:07 +08:00
RISCVInstrFormats.td [VENTUS][fix] Add memory access flags in tablegen 2024-06-14 09:46:00 +08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td [RISCV] Replace hardcoded constant with OPIVI.Value in tablegen. NFC 2022-11-30 20:58:40 -08:00
RISCVInstrInfo.cpp [VENTUS][fix] Add memory access flags in tablegen 2024-06-14 09:46:00 +08:00
RISCVInstrInfo.h [VENTUS][fix] Put local variables declared in kernel function into shared memory 2024-03-05 16:32:59 +08:00
RISCVInstrInfo.td [VENTUS][RISCV][fix] Constraint divergent private load/store instructions can only use tp register 2023-04-27 09:32:25 +08:00
RISCVInstrInfoA.td [RISCV] Add target feature to force-enable atomics 2022-08-09 16:04:46 +02:00
RISCVInstrInfoC.td Add MC support of RISCV Zcd Extension 2022-11-24 05:48:06 +08:00
RISCVInstrInfoD.td Propagate uniform execution predicates to all Ventus sALU operations. 2022-12-16 14:04:55 +08:00
RISCVInstrInfoF.td Update customized instructions' encoding 2023-02-24 11:21:19 +08:00
RISCVInstrInfoM.td [RISCV][Clang] Add support for Zmmul extension 2022-07-18 20:26:08 -04:00
RISCVInstrInfoV.td [VENTUS][RISCV][test&fix] Add more MC test and fix related bugs 2023-07-11 11:17:55 +08:00
RISCVInstrInfoVPseudos.td [RISCV][Codegen] Account for LMUL in Vector floating-point instructions 2022-11-30 11:09:21 -08:00
RISCVInstrInfoVSDPatterns.td [RISCV] Use _TIED form of VFWADD(U)_WV/VFWSUB(U)_WV to avoid early clobber. 2022-10-03 21:44:08 -07:00
RISCVInstrInfoVVLPatterns.td [VP][RISCV] Add vp.nearbyint and RISC-V support. 2022-11-16 14:05:35 +08:00
RISCVInstrInfoXVentana.td [RISCV] Implement assembler support for XVentanaCondOps 2022-11-14 09:01:54 -08:00
RISCVInstrInfoZb.td [VENTUS][RISCV] Fix rd,rs1,rs2,rs3 register ordering in regext insertion pass. 2023-07-06 11:47:34 +08:00
RISCVInstrInfoZfh.td Propagate uniform execution predicates to all Ventus sALU operations. 2022-12-16 14:04:55 +08:00
RISCVInstrInfoZicbo.td [VENTUS][RISCV] Fix rd,rs1,rs2,rs3 register ordering in regext insertion pass. 2023-07-06 11:47:34 +08:00
RISCVInstrInfoZk.td
…
RISCVMCInstLower.cpp Very very early step to remove RVV features from code base. 2022-12-16 17:33:54 +08:00
RISCVMachineFunctionInfo.cpp Update Ventus GPGPU ABI: X4 as stack pointer, V0-V31 as arguments registers etc 2022-12-28 13:11:22 +08:00
RISCVMachineFunctionInfo.h [VENTUS][RISCV][fix] Modify calling convention 2023-06-05 17:11:25 +08:00
RISCVMacroFusion.cpp [RISCV] Be more strict about LUI+ADDI macrofusion pre-RA. 2022-08-21 10:58:15 -07:00
RISCVMacroFusion.h [RISCV] Add macrofusion infrastructure and one example usage. 2022-06-23 08:38:39 -07:00
RISCVMakeCompressible.cpp [VENTUS][fix] Remove instructions not supported by hardware 2023-11-24 17:26:50 +08:00
RISCVMergeBaseOffset.cpp [VENTUS][fix] Remove instructions not supported by hardware 2023-11-24 17:26:50 +08:00
RISCVRedundantCopyElimination.cpp [RISCV] Use analyzeBranch in RISCVRedundantCopyElimination. 2022-08-29 09:05:53 -07:00
RISCVRegisterInfo.cpp [Ventus][fix]Fix missing vmv instruction for FrameReg in divergent path 2024-06-06 16:16:57 +08:00
RISCVRegisterInfo.h [VENTUS][fix]Fix kernel divergent analysis 2024-04-22 15:53:36 +08:00
RISCVRegisterInfo.td [RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI 2022-08-24 14:16:20 +00:00
RISCVSExtWRemoval.cpp [VENTUS][fix] Comment out illegal fmv.w.x instruction and change vmv instructions' format 2023-10-09 14:04:55 +08:00
RISCVSchedRocket.td [RISCV] Merge WriteLDW and WriteLDWU schedule classes. 2022-10-28 11:57:33 -07:00
RISCVSchedSiFive7.td [RISCV] Merge WriteLDW and WriteLDWU schedule classes. 2022-10-28 11:57:33 -07:00
RISCVSchedule.td [RISCV] Merge WriteLDW and WriteLDWU schedule classes. 2022-10-28 11:57:33 -07:00
RISCVScheduleV.td [RISCV][Codegen] Account for LMUL in Vector floating-point instructions 2022-11-30 11:09:21 -08:00
RISCVScheduleZb.td [RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC 2022-09-23 21:38:42 -07:00
RISCVSearchableTables.td Drafting divergent related code, not working yet. 2022-12-19 18:11:34 +08:00
RISCVSubtarget.cpp Very very early step to remove RVV features from code base. 2022-12-16 17:33:54 +08:00
RISCVSubtarget.h [VENTUS][fix] Distinguish the resource usage of each kernel function 2023-12-14 17:18:20 +08:00
RISCVSystemOperands.td [VENTUS][RISCV] Fix insert setrpc/join instruction pass for VBranch. 2023-06-27 16:02:01 +08:00
RISCVTargetMachine.cpp [VENTUS][fix] Legalize vlw12.v instruction for variadic functions 2023-09-07 16:39:11 +08:00
RISCVTargetMachine.h Add OpenCL addressing space mapping to RISCVAS. 2022-12-20 17:08:08 +08:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp [VENTUS][fix]Fix kernel divergent analysis 2024-04-22 15:53:36 +08:00
RISCVTargetTransformInfo.h [VENTUS][RISCV][fix] Add more divergence ananlysis 2023-06-15 22:34:40 +08:00
VentusCallingConv.td [Ventus] ABI and stack adjustment. 2023-06-21 13:08:02 +08:00
VentusInsertJoinToVBranch.cpp [VENTUS][RISCV] Fix move instructions after JOIN move forward bug 2024-03-29 16:15:12 +08:00
VentusInstrFormatsV.td [VENTUS][fix] Support the regexti instruction 2024-01-23 09:59:51 +08:00
VentusInstrInfo.td [VENTUS][fix] Fix memory flags set in tablegen #129 2024-06-24 23:01:47 +08:00
VentusInstrInfoA.td [VENTUS][RISCV][feat] Add atomic instructions VGPR index support 2023-07-24 13:38:42 +08:00
VentusInstrInfoC.td [VENTUS][RISCV][feat] Add zfinx support 2023-04-23 11:29:09 +08:00
VentusInstrInfoF.td [VENTUS][workaround] Fix flw/fsw assembly errors 2024-04-26 15:14:22 +08:00
VentusInstrInfoM.td Propagate uniform execution predicates to all Ventus sALU operations. 2022-12-16 14:04:55 +08:00
VentusInstrInfoV.td [VENTUS][fix] Fix memory flags set in tablegen #129 2024-06-24 23:01:47 +08:00
VentusInstrInfoVPseudos.td [VENTUS][fix] Deprecating vmv.s.x and use vmv.v.x instead 2023-08-01 13:25:24 +08:00
VentusInstrInfoVSDPatterns.td Copy RVV codegen pattern related file RISCVInstrInfo*.td to VentusInstrInfo*.td. 2022-12-15 17:04:09 +08:00
VentusInstrInfoVVLPatterns.td Copy RVV codegen pattern related file RISCVInstrInfo*.td to VentusInstrInfo*.td. 2022-12-15 17:04:09 +08:00
VentusLegalizeLoad.cpp [VENTUS][NFC] Update comments 2023-09-07 22:18:13 +08:00
VentusProgramInfo.h [VENTUS][fix] Distinguish the resource usage of each kernel function 2023-12-14 17:18:20 +08:00
VentusRegextInsertion.cpp [VENTUS][fix]Fix missing regext instruction for vmsle instruction 2024-05-21 17:09:48 +08:00
VentusRegisterInfo.td [VENTUS][fix]Fix kernel divergent analysis 2024-04-22 15:53:36 +08:00
VentusVVInstrConversion.cpp [VENTUS][RISCV][NFC] Disable conversion for floating VV instrcution convertion 2023-06-29 14:28:02 +08:00