Commit Graph

1642 Commits

Author SHA1 Message Date
Jules-Kong 6f23d8d54a [VENTUS][NFC] Removed old implementations of some builtin functions 2025-03-14 10:46:42 +08:00
Mifuns e4c88939fe
[#60][feat] Support barrier with memory scope parameter (#63)
Co-authored-by: qinfan <qinfan.wang@terapines.com>
2023-11-22 16:02:16 +08:00
zhoujing 198eea9938 [VENTUS][feat] Support varadic function && enable address space in vastart/vaend 2023-08-08 15:45:41 +08:00
zhoujingya 553e65dcf7 Change barrier and work_group_barrier into builtin functions 2023-03-14 10:38:22 +08:00
zhoujing a92723f212 Update barrier intrinsics' name and modify barrier's encoding 2023-02-10 14:50:40 +08:00
zhoujing 59ec313359 Add riscv builtin support for opencl barrier function 2023-02-09 17:53:15 +08:00
Aries c0ccb59e9f WORKAROUND: Fix libclc building error 2023-01-16 16:05:08 +08:00
Aries dee3135130 Drafting divergent related code, not working yet. 2022-12-19 18:11:34 +08:00
Kazu Hirata bb666c6930 [CodeGen] Use std::nullopt instead of None (NFC)
This patch mechanically replaces None with std::nullopt where the
compiler would warn if None were deprecated.  The intent is to reduce
the amount of manual work required in migrating from Optional to
std::optional.

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-03 11:13:43 -08:00
gonglingqin 624401612c [LoongArch] Add remaining intrinsics for CRC check instructions
After D137316 implements the intrinsics of the first crc check instruction
and related diagnosis, this patch implements the intrinsics of all remaining
crc check instructions.

Differential Revision: https://reviews.llvm.org/D138418
2022-12-01 09:40:50 +08:00
Krzysztof Parzyszek b805853ccb [Hexagon] Make local array static in getIntrinsicForHexagonNonClangBuiltin
It should not be created on every call, the omission of `static` was a bug
in the patch that introduced it.
2022-11-22 09:48:01 -08:00
Thomas Lively ae96b5bd2d [WebAssembly] Update relaxed-simd instruction names
Including builtin and intrinsic names. These should be the final names for the
proposal.
https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md

Reviewed By: aheejin, maratyszcza

Differential Revision: https://reviews.llvm.org/D138249
2022-11-21 12:40:15 -08:00
gonglingqin c2ec455f18 [LoongArch] Add intrinsics for ibar, break and syscall
Diagnostics for intrinsic input parameters have also been added.

Differential Revision: https://reviews.llvm.org/D138094
2022-11-21 09:31:26 +08:00
Xing Xue fa7477eb87 [Clang][CodeGen][AIX] Map __builtin_frexpl, __builtin_ldexpl, and __builtin_modfl to 'double' version lib calls in 64-bit 'long double' mode
Summary:
AIX library functions frexpl(), ldexpl(), and modfl() are for 128-bit IBM long double, i.e. __ibm128. Other *l() functions, e.g., acosl(), are for 64-bit long double. The AIX Clang compiler currently maps builtin functions __builtin_frexpl(), __builtin_ldexpl(), and __builtin_modfl() to frexpl(), ldexpl(), and modfl() in 64-bit long double mode which results in seg-faults or incorrect return values. This patch changes to map __builtin_frexpl(), __builtin_ldexpl(), and __builtin_modfl() to double version lib functions frexp(), ldexp() and modf() in 64-bit long double mode.

Reviewed by: hubert.reinterpretcast, daltenty

Differential Revision: https://reviews.llvm.org/D137986
2022-11-18 11:36:56 -05:00
Joshua Batista a5d14f757b Add builtin_elementwise_sin and builtin_elementwise_cos
Add codegen for llvm cos and sin elementwise builtins
The sin and cos elementwise builtins are necessary for HLSL codegen.
Tests were added to make sure that the expected errors are encountered
when these functions are given inputs of incompatible types.
The new builtins are restricted to floating point types only.

Reviewed By: craig.topper, fhahn

Differential Revision: https://reviews.llvm.org/D135011
2022-11-10 23:30:27 -08:00
gonglingqin da34aff90d [Clang][LoongArch] Implement __builtin_loongarch_crc_w_d_w builtin and add diagnostics
This patch adds support to prevent __builtin_loongarch_crc_w_d_w from compiling
on loongarch32 in the front end and adds diagnostics accordingly.

Reference: https://github.com/gcc-mirror/gcc/blob/master/gcc/config/loongarch/larchintrin.h#L175-L184

Depends on D136906

Differential Revision: https://reviews.llvm.org/D137316
2022-11-11 09:16:57 +08:00
gonglingqin 85f08c4197 [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin
Differential Revision: https://reviews.llvm.org/D136906
2022-11-10 17:27:44 +08:00
Freddy Ye a806fc2767 [X86] Support -march=raptorlake, meteorlake
Reviewed By: pengfei, skan, MaskRay

Differential Revision: https://reviews.llvm.org/D135937
2022-11-04 09:32:17 +08:00
Krzysztof Parzyszek 13918432cf [Hexagon] Add builtins and intrinsics for V6_v[add|sub]carryo 2022-10-31 13:41:31 -07:00
David Green af1bb287b4 [AArch64][ARM] Alter v8.3a complex neon intrinsics to be target-based, not preprocessor based
This alters the 8.3 complex intrinsics to be target-gated, as opposed to
hidden behind preprocessor macros. This is the last of arm_neon.h, and
follows the same formula as before.

Differential Revision: https://reviews.llvm.org/D135647
2022-10-25 14:35:11 +01:00
David Green 9c48b7f0e7 [AArch64][ARM] Alter v8.1a neon intrinsics to be target-based, not preprocessor based
As a continuation of D132034, this switches the QRDMX v8.1a neon
intrinsics over from preprocessor defines to be target-gated. As there
is no "rdma" or "qrdmx" target feature, they use the "v8.1a"
architecture feature directly.

This works well for AArch64, but something needs to be done for Arm at
the same time, as they both use the same header and tablegen emitter.
This patch opts for adding "v8.1a" and all dependant target features to
the Arm TargetParser, similar to what was recently done for AArch64 but
through initFeatureMap when the Architecture is parsed. I attempted to
make the code similar to the AArch64 backend.

Otherwise this is similar to the changes made in D132034.

Differential Revision: https://reviews.llvm.org/D135615
2022-10-25 09:02:52 +01:00
Markus Böck 3637dc601c [clang][CodeGen] Consistently return nullptr Values for void builtins and scalar initalization
A common post condition of the various visitor functions in CodeGen is that instructions, that do not return any values, simply return a nullptr Value as a sentinel. This has not been the case however for calls to some builtins returning void, as well as for an initializer expression of the form `void()`. This would then lead to ICEs in CodeGen on code relying on nullptr being returned for void values, which is eg. the case for conditional expressions [0].
This patch fixes that by returning nullptr Values for intrinsics known not to return any values as well as for a scalar initializer returning void.

Fixes https://github.com/llvm/llvm-project/issues/53127

[0] 266ec801fb/clang/lib/CodeGen/CGExprScalar.cpp (L4849-L4892)

Differential Revision: https://reviews.llvm.org/D136548
2022-10-24 21:41:13 +02:00
David Green 6f1e430360 [AArch64] Alter v8.5a FRINT neon intrinsics to be target-based, not preprocessor based
This switches the v8.5-a FRINT intrinsics over to be target-gated,
behind preprocessor defines. This one is pretty simple, being AArch64
only.

Differential Revision: https://reviews.llvm.org/D135646
2022-10-24 11:22:06 +01:00
Paulo Matos 39d8597927 [clang] Fix typo in error message 2022-10-21 12:06:28 +02:00
Phoebe Wang 62ca79102c [X86][1/2] Support PREFETCHI instructions
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D136040
2022-10-20 08:46:01 +08:00
Phoebe Wang bc1819389f [X86][RFC] Using `__bf16` for AVX512_BF16 intrinsics
This is an alternative of D120395 and D120411.

Previously we use `__bfloat16` as a typedef of `unsigned short`. The
name may give user an impression it is a brand new type to represent
BF16. So that they may use it in arithmetic operations and we don't have
a good way to block it.

To solve the problem, we introduced `__bf16` to X86 psABI and landed the
support in Clang by D130964. Now we can solve the problem by switching
intrinsics to the new type.

Reviewed By: LuoYuanke, RKSimon

Differential Revision: https://reviews.llvm.org/D132329
2022-10-19 23:47:04 +08:00
David Green b879f99f0e [AArch64][ARM] Alter most of arm_neon.h to be target-based, not preprocessor based.
Similar to D131064, this alters most of the intrinsics in arm_neon.h to
be target based, not preprocessor based. The intrinsics that are changed
are the ones with obvious target features (fp16, fp16fml, cryptos, i8mm
and bf16). The ones that are not yet altered are the ones without target
features like rdma (8.1) and complex (8.3). Those will be switched in a
followup patch that allows targeting architecture versions.

The existing ArchGuard in arm_neon.td is split into ArchGuard that still
adds ifdef defines (for example for intrinsics that require __aarch64__),
and TargetGuards for intrinsics dependant on target features. From there
the TargetGuards are used in two ways:
 - For intrinsics emitted as functions, __attribute__((target(TargetGuard)))
   is added to the definition of the function. Along with the existing
   always_inline intrinsic, this will give a compile time error if the
   function is used in a context where the target feature is not available.
 - For intrinsics emitted as macros, the __builtins are emitted into
   arm_neon.inc using TARGET_BUILTIN as opposed to BUILTIN, which includes
   the target feature and gives an error if the builtin is found in a
   function without the required features, similar to arm_sve.h.

The second method requires that the intrinsics be separable from the
existing _v intrinsics used in other types. For example
__builtin_neon_splat_lane_bf16 is used as opposed to
__builtin_neon_splat_lane_v. There are some adjustments to the CGBuiltin
to account for intrinsics that can be treated similarly, except for
their target features.

Differential Revision: https://reviews.llvm.org/D132034
2022-10-11 09:09:16 +01:00
Manuel Brito 14e2592ff6 [clang][CodeGen] Use poison instead of undef as placeholder in ARM builtins [NFC]
Differential Revision: https://reviews.llvm.org/D135392
2022-10-07 12:50:59 +01:00
Michael Platings dba8fced96 Fix frint ACLE intrinsic names
Although the instruction names begin "frint", the ACLE spec states that
the intrinsic names begin "__rint", without the "f".

Differential Revision: https://reviews.llvm.org/D134824
2022-09-29 09:13:07 +01:00
eopXD 10409bf86e [FPEnv] Remove inaccurate comments regarding signaling NaN for isless
By draft of C23 (https://www.open-std.org/jtc1/sc22/wg14/www/docs/n2912.pdf),
the description for isless macro under 7.12.17.3 says,

The isless macro determines whether its first argument is less than its second
argument. The value of isless(x,y) is always equal to (x)< (y); however, unlike
(x) < (y), isless(x,y) does not raise the invalid floating-point exception when
x and y are unordered and neither is a signaling NaN.

isless should trap when encountering signaling NaN.

Reviewed By: jcranmer-intel, efriedma

Differential Revision: https://reviews.llvm.org/D134407
2022-09-22 18:13:16 -07:00
Craig Topper 52708be182 [RISCV] Remove support for the unratified Zbe, Zbf, and Zbm extensions.
These extensions do not appear to be on their way to ratification.
2022-09-22 13:04:41 -07:00
Craig Topper 182aa0cbe0 [RISCV] Remove support for the unratified Zbp extension.
This extension does not appear to be on its way to ratification.

Still need some follow up to simplify the RISCVISD nodes.
2022-09-21 21:22:42 -07:00
Chuanqi Xu 327141fb1d [C++] [Coroutines] Prefer aligned (de)allocation for coroutines -
implement the option2 of P2014R0

This implements the option2 of
https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p2014r0.pdf.

This also fixes https://github.com/llvm/llvm-project/issues/56671.

Although wg21 didn't get consensus for the direction of the problem,
we're happy to have some implementation and user experience first. And
from issue56671, the option2 should be the pursued one.

Reviewed By: ychen

Differential Revision: https://reviews.llvm.org/D133341
2022-09-22 11:28:29 +08:00
Craig Topper 70a64fe7b1 [RISCV] Remove support for the unratified Zbt extension.
This extension does not appear to be on its way to ratification.

Out of the unratified bitmanip extensions, this one had the
largest impact on the compiler.

Posting this patch to start a discussion about whether we should
remove these extensions. We'll talk more at the RISC-V sync meeting this
Thursday.

Reviewed By: asb, reames

Differential Revision: https://reviews.llvm.org/D133834
2022-09-20 20:26:48 -07:00
Stanislav Mekhanoshin e540965915 [AMDGPU] Added __builtin_amdgcn_ds_bvh_stack_rtn
Differential Revision: https://reviews.llvm.org/D133966
2022-09-16 02:42:09 -07:00
Thomas Lively ac3b8df8f2 [WebAssembly] Prototype `f32x4.relaxed_dot_bf16x8_add_f32`
As proposed in https://github.com/WebAssembly/relaxed-simd/issues/77. Only an
LLVM intrinsic and a clang builtin are implemented. Since there is no bfloat16
type, use u16 to represent the bfloats in the builtin function arguments.

Differential Revision: https://reviews.llvm.org/D133428
2022-09-08 08:07:49 -07:00
yronglin 6ed21fc515 Avoid __builtin_assume_aligned crash when the 1st arg is array type
Avoid __builtin_assume_aligned crash when the 1st arg is array type (or
string literal).

Fixes Issue #57169

Differential Revision: https://reviews.llvm.org/D133202
2022-09-07 12:46:20 -04:00
Vitaly Buka 9905dae5e1 Revert "[Clang][CodeGen] Avoid __builtin_assume_aligned crash when the 1st arg is array type"
Breakes windows bot.

This reverts commit 3ad2fe913a.
2022-09-03 13:12:49 -07:00
Kazu Hirata 89f1433225 Use llvm::lower_bound (NFC) 2022-09-03 11:17:37 -07:00
yronglin 3ad2fe913a [Clang][CodeGen] Avoid __builtin_assume_aligned crash when the 1st arg is array type
Avoid __builtin_assume_aligned crash when the 1st arg is array type(or string literal).

Open issue: https://github.com/llvm/llvm-project/issues/57169

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D133202
2022-09-03 23:26:01 +08:00
Chuanqi Xu 7e19d53da4 [NFC] Emit builtin coroutine calls uniforally
All the coroutine builtins were emitted in EmitCoroutineIntrinsic except
__builtin_coro_size. This patch tries to emit all the corotine builtins
uniformally.
2022-09-01 16:31:51 +08:00
Kazu Hirata 86bc4587e1 Use std::clamp (NFC)
This patch replaces clamp idioms with std::clamp where the range is
obviously valid from the source code (that is, low <= high) to avoid
introducing undefined behavior.
2022-08-27 09:53:13 -07:00
Yaxun (Sam) Liu 9f6cb3e9fd [AMDGPU] Add builtin s_sendmsg_rtn
Reviewed by: Brian Sumner, Artem Belevich

Differential Revision: https://reviews.llvm.org/D132140

Fixes: SWDEV-352017
2022-08-22 18:29:23 -04:00
Caroline Concatto 9f21d6e953 [Clang][AArch64] Use generic extract/insert vector for svget/svset/svcreate tuples
This patch replaces svget, svset and svcreate aarch64 intrinsics for tuple
types with the generic llvm-ir intrinsics extract/insert vector

Differential Revision: https://reviews.llvm.org/D131547
2022-08-19 12:58:59 +01:00
Caroline Concatto 4ef1f014a1 [Clang][AArch64] Replace aarch64_sve_ldN intrinsic by aarch64_sve_ldN.sret
Differential Revision: https://reviews.llvm.org/D131687
2022-08-19 11:42:18 +01:00
Florian Hahn ef110a491f
[Builtins] Do not claim most libfuncs are readnone with trapping math.
At the moment, Clang only considers errno when deciding if a builtin
is const. This ignores the fact that some library functions may raise
floating point exceptions, which may modify global state, e.g. when
updating FP status registers.

To model the fact that some library functions/builtins may raise
floating point exceptions, this patch adds a new 'g' modifier for
builtins. If a builtin is marked with 'g', it cannot be considered
const, unless FP exceptions are ignored.

So far I've not added CHECK lines for all calls in math-libcalls.c. I'll
do that once we agree on the overall direction.

A consequence seems to be that we fail to select some of the constrained
math builtins now, but I am not entirely sure what's going on there.

Reviewed By: john.brawn

Differential Revision: https://reviews.llvm.org/D129231
2022-08-11 12:29:01 +01:00
Fangrui Song 3f18f7c007 [clang] LLVM_FALLTHROUGH => [[fallthrough]]. NFC
With C++17 there is no Clang pedantic warning or MSVC C5051.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D131346
2022-08-08 09:12:46 -07:00
Matt Arsenault c5b36ab1d6 AMDGPU/clang: Remove dead code
The order has to be a constant and should be enforced by the builtin
definition. The fallthrough behavior would have been broken anyway.

There's still an existing issue/assert if you try to use garbage for the
ordering. The IRGen should be broken, but we also hit another assert
before that.

Fixes issue 56832
2022-08-04 19:02:56 -04:00
Zakk Chen 71fd66161d [RISCV][Clang] Support RVV policy functions.
1. Add policy functions support and tests for vadd, vmv, vfmv and all load
   instructions except segment load. I didn't add all combination of policy
   functions in test because it seem not to make sense.
2. Rename HasUnMaskedOverloaded to SupportOverloading.
3. vmv.s.x for ta policy could not have overloaded API.
4. This patch does not support all operations, I will have other follow-up
   patches support all.

[RFC] https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/137

Reviewed By: kito-cheng, fakepaper56, fakepaper56

Differential Revision: https://reviews.llvm.org/D126742
2022-08-01 17:32:08 +00:00
Gabriel Ravier 5674a3c880 Fixed a number of typos
I went over the output of the following mess of a command:

(ulimit -m 2000000; ulimit -v 2000000; git ls-files -z |
 parallel --xargs -0 cat | aspell list --mode=none --ignore-case |
 grep -E '^[A-Za-z][a-z]*$' | sort | uniq -c | sort -n |
 grep -vE '.{25}' | aspell pipe -W3 | grep : | cut -d' ' -f2 | less)

and proceeded to spend a few days looking at it to find probable typos
and fixed a few hundred of them in all of the llvm project (note, the
ones I found are not anywhere near all of them, but it seems like a
good start).

Differential Revision: https://reviews.llvm.org/D130827
2022-08-01 13:13:18 -04:00