OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 2
Code Issues Packages Projects Releases Wiki Activity

WORKAROUND: Fix libclc building error

This commit is contained in:
Aries 2023-01-16 16:05:08 +08:00
parent f933867e85
commit c0ccb59e9f
2 changed files with 6 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
clang/include/clang/Basic/BuiltinsRISCV.def
View File

@ -18,7 +18,8 @@
//===----------------------------------------------------------------------===//
// Ventus OpenCL builtins.
//===----------------------------------------------------------------------===//
// WORKAROUND: Disabled for now.
/*
BUILTIN(__builtin_riscv_workgroup_id_x, "Ui", "nc")
BUILTIN(__builtin_riscv_workgroup_id_y, "Ui", "nc")
BUILTIN(__builtin_riscv_workgroup_id_z, "Ui", "nc")
@ -34,7 +35,7 @@ BUILTIN(__builtin_riscv_workgroup_size_z, "Us", "nc")
BUILTIN(__builtin_riscv_grid_size_x, "Ui", "nc")
BUILTIN(__builtin_riscv_grid_size_y, "Ui", "nc")
BUILTIN(__builtin_riscv_grid_size_z, "Ui", "nc")
*/
//===----------------------------------------------------------------------===//
// Standard RISCV instruction builtins.
//===----------------------------------------------------------------------===//

5
clang/lib/CodeGen/CGBuiltin.cpp
View File

@ -19461,6 +19461,8 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
switch (BuiltinID) {
default: llvm_unreachable("unexpected builtin ID");
// WORKAROUND: Disabled for now.
/*
// Ventus GPGPU workitem
case RISCV::BI__builtin_riscv_workitem_id_x:
return emitRangedBuiltin(*this, Intrinsic::riscv_workitem_id_x, 0, 1024);
@ -19470,7 +19472,6 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
return emitRangedBuiltin(*this, Intrinsic::riscv_workitem_id_z, 0, 1024);
// FIXME: Use AMDGPU function here temporarily
// Ventus GPGPU workgroup size
case RISCV::BI__builtin_riscv_workgroup_size_x:
return EmitAMDGPUWorkGroupSize(*this, 0);
@ -19486,7 +19487,7 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
return EmitAMDGPUGridSize(*this, 1);
case RISCV::BI__builtin_riscv_grid_size_z:
return EmitAMDGPUGridSize(*this, 2);
*/
case RISCV::BI__builtin_riscv_orc_b_32:
case RISCV::BI__builtin_riscv_orc_b_64:
case RISCV::BI__builtin_riscv_clz_32: