1.Fix errors in VALUrVV class(llvm/lib/Target/RISCV/VentusInstrInfoV.td) where two source operand positions were reversed,
this is differnt from the conventional RISCV instruction.
2.Fix errors in VALUrVF class, same as above.
3.The instructions associated with the above two errors are "vfnmadd.vv", "vfnmadd.vf", etc.
4.Add MC level FileCheck test files to test V instructions.
The patch is split from D103435. The patch supported a new directive .variant_cc
that annotates function with STO_RISCV_VARIANT_CC. Symbols marked with
STO_RISCV_VARIANT_CC do not use standard calling conversion or use parameter not
passed in GPR/FPR.
Related: https://github.com/riscv/riscv-elf-psabi-doc/pull/190
Initial authored by: HsiangKai
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D138352
This part is not useful (all the custom parsing deals with directives) and does
not appear in the majority of diagnostics.
While updating diagnostics, change "unexpected token" to more useful
diagnostics, e.g. "expected comma", "expected end of directive".
Extends the Asm reader/writer to support reading and writing the
'.memtag' directive (including allowing it on internal global
variables). Also add some extra tooling support, including objdump and
yaml2obj/obj2yaml.
Test that the sanitize_memtag IR attribute produces the expected asm
directive.
Uses the new Aarch64 MemtagABI specification
(https://github.com/ARM-software/abi-aa/blob/main/memtagabielf64/memtagabielf64.rst)
to identify symbols as tagged in object files. This is done using a
R_AARCH64_NONE relocation that identifies each tagged symbol, and these
relocations are tagged in a special SHT_AARCH64_MEMTAG_GLOBALS_STATIC
section. This signals to the linker that the global variable should be
tagged.
Reviewed By: fmayer, MaskRay, peter.smith
Differential Revision: https://reviews.llvm.org/D128958
Add ELFObjectFileBase::getLoongArchFeatures, and return the proper ELF
relative reloc type for LoongArch.
Reviewed By: MaskRay, SixWeining
Differential Revision: https://reviews.llvm.org/D138016
Virtual Memory System Architecture (VMSA)
This is part of the 2022 A-Profile Architecture extensions and adds support for
the following:
- Translation Hardening Extension (FEAT_THE)
- 128-bit Page Table Descriptors (FEAT_D128)
- 56-bit Virtual Address (FEAT_LVA3)
- Support for 128-bit System Registers (FEAT_SYSREG128)
- System Instructions that can take 128-bit inputs (FEAT_SYSINSTR128)
- 128-bit Atomic Instructions (FEAT_LSE128)
- Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
- Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
- Memory Attribute Index Enhancement (FEAT_AIE)
New instructions added:
- FEAT_SYSREG128 adds MRRS and MSRR.
- FEAT_SYSINSTR128 adds the SYSP instruction and TLBIP aliases.
- FEAT_LSE128 adds LDCLRP, LDSET, and SWPP instructions.
- FEAT_THE adds the set of RCW* instructions.
Specs for individual instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/
Contributors:
Keith Walker
Lucas Prates
Sam Elliott
Son Tuan Vu
Tomas Matheson
Differential Revision: https://reviews.llvm.org/D138920
In revision B.q and before of the Armv8-M architecture reference
manual, the vector/scalar forms of the `vmla` and `vmlas` instructions
came in signed and unsigned integer forms, such as `vmla.s8 q0,q1,r2`
or `vmlas.u32 q3,q4,r5`.
Revision B.r has changed this. There are no longer signed and unsigned
versions of these instructions, since they were functionally identical
anyway. Now there is just `vmla.i8` (or `i16` or `i32`, and similarly
for `vmlas`). Bit 28 of the instruction encoding, which was previously
0 for signed or 1 for unsigned, is now expected to be 0 always.
This change updates LLVM to the new version of the architecture. The
obsoleted encodings for unsigned integers are now decoding errors, and
only the still-valid encoding is ever emitted. This shouldn't break
any existing assembly code, because the old signed and unsigned
versions of the mnemonic are still accepted by the assembler (which is
standard practice anyway for all signedness-agnostic MVE integer
instructions).
Reviewed By: dmgreen, lenary
Differential Revision: https://reviews.llvm.org/D138827
avr-gcc uses the $ symbol as an assembly separator instead of the more
common %% syntax. We need it in LLVM too to be compatible.
Differential Revision: https://reviews.llvm.org/D138535
This patch implements assembly support for the 2022 A-Profile Architecture
extension FEAT_LRCPC3. FEAT_LRCPC3 is AArch64 only and introduces new
variants of load/store instructions with release consistency ordering.
Specs for individual instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/
This feature is optionally available from v8.2a and therefore not enabled by
default.
Contributors:
Lucas Prates
Sam Elliot
Son Tuan Vu
Tomas Matheson
Differential Revision: https://reviews.llvm.org/D138579
The following system registers have been missing upstream:
- ID_DFR1_EL1
- AMCG1IDR_EL0 (present when FEAT_AMUv1p1 implemented - optional from v8.6-a)
- HAFGRTR_EL2 (present when FEAT_AMUv1 and FEAT_FGT are implemented)
With regards to HAFGRTR_EL2, this is only present when you have both
extensions. As FEAT_FGT is part of a later architecture, we group it
with those registers. In all honesty, this is a good example of the
kinds of place where just enabling all system registers all the time
would be easiest.
Differential Revision: https://reviews.llvm.org/D138553
This adds support for the 2022 Debug and PMU extensions that are part of
the v8.9-A and v9.4-A architecture versions. This includes:
* New archtecture extension for the v9.4-A Instrumentation Extension
(FEAT_ITE), including 'trcit' instruction and system registers
* New system registers for:
* 2022 Debug features (FEAT_Debugv8p9)
* 2022 Performance Monitors Extension features (FEAT_PMUv3p9)
* PMU Snapshot extension (FEAT_PMUv3_SS)
* PMU Fixed-function instruction counter (FEAT_PMUv3_ICNTR)
* System Performance Monitors Extension (FEAT_SPMU)
* Synchornous-exception-based event profiling (FEAT_SEBEP)
* Fine Grained Traps Extension (FEAT_FGT2)
* SPE Data Source filtering (FEAT_SPE_FDS)
More information on the new extensions can be found on:
* https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022
* https://developer.arm.com/downloads/-/exploration-tools
Changes by Son Tuan Vu, Sam Elliott and me.
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D138556
Eliminates the need for working around optional and token operands being
mistakenly parsed as expressions.
Reviewed By: dp
Differential Revision: https://reviews.llvm.org/D138492
This patch add the instructions of Zcd extension.
Zcd is a subset of C Ext which include the double-precision floating-point instructions (c.fld, c.fldsp, c.fsd, c.fsdsp).
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D134177
This patch add the instructions of Zcf extension.
Zcf is a subset of C Ext which include the single-precision floating-point instructions.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D134176
This patch implements the 2022 Architecture General Data-Processing Instructions
They include:
Common Short Sequence Compression (CSSC) instructions
- scalar comparison instructions
SMAX, SMIN, UMAX, UMIN (32/64 bits) with or without immediate
- ABS (absolute), CNT (count non-zero bits), CTZ (count trailing zeroes)
- command-line options for CSSC
Associated with these instructions in the documentation is the Range Prefetch
Memory (RPRFM) instruction, which signals to the memory system that data memory
accesses from a specified range of addresses are likely to occur in the near
future. The instruction lies in hint space, and is made unconditional.
Specs for the individual instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/
contributors to this patch:
- Cullen Rhodes
- Son Tuan Vu
- Mark Murray
- Tomas Matheson
- Sam Elliott
- Ties Stuij
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D138488
Add missing assembler/disassembler tests for INSTID_SALU_CYCLE_2
and INSTID_SALU_CYCLE_3 which are possible arguments in S_DELAY_ALU.
Differential Revision: https://reviews.llvm.org/D138482
This patch add the support of RISCV Zca ext
`Zca` is a subset of C extension instructions that are compatible with the Zc extension.
So this patch implements Zca code generation with reference to the C extension and sets the 2-byte alignment for the Zca extension, just like C extension does.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D130483
The `li.[wd]` pseudo instructions are used to load an immediate value
into a GPR. These expand directly during asm parsing. As the result,
only real MC instructions are emitted to the MCStreamer. The actual
expansion to real instructions is similar to the expansion performed by
the GAS.
Note: The `li.w` always treats the imm operand as a 32-bit signed value.
Reviewed By: SixWeining
Differential Revision: https://reviews.llvm.org/D138086
This patch makes `IAS` compatible with `GAS`. It accepts `la*` pseudo
instructions, and expands `la{,.local,.global}` into different
instructions according to different features.
```
Default:
la = la.global = la.got
la.local = la.pcrel
With feature "+la-global-with-pcrel":
la = la.global = la.pcrel
With feature "+la-global-with-abs":
la = la.global = la.abs
With feature "+la-local-with-abs":
la.local = la.abs
With features "+la-global-with-pcrel,+la-global-with-abs"(disorder):
la = la.global = la.pcrel
```
Note: To keep consistent with `GAS` behavior, the "la" can only have
one register operand.
Reviewed By: SixWeining
Differential Revision: https://reviews.llvm.org/D138021
These instructions always output the canonical mnemonic. The GNU tools
emit the canonical mnemonic for the branch pseudo instructions as well
(e.g. "bgt" will be recognised by the assembler but never printed by
objdump).
Reviewed By: xen0n
Differential Revision: https://reviews.llvm.org/D138100
D136149 and D136148 renamed the MC test files for VOP3 promoted from VOP1 and
VOP2 in a consistent way. Do the same for VOP3 coming from VOPC.
Reviewed By: dp
Differential Revision: https://reviews.llvm.org/D137950
zhoujing
qinfan