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[AArch64][NFC] SME2 Add missing tests for usvdot and sumlall instructions

This commit is contained in:
Caroline Concatto 2022-11-21 17:27:48 +00:00
parent 7f37a779e9
commit c0414518f1
3 changed files with 653 additions and 795 deletions
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1227
llvm/test/MC/AArch64/SME2/sumlall.s
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llvm/test/MC/AArch64/SME2/usvdot-diagnostics.s Normal file
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Out of range index offset
usvdot za.s[w8, 8, vgx4], {z0.b-z3.b}, z0.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: usvdot za.s[w8, 8, vgx4], {z0.b-z3.b}, z0.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usvdot za.s[w8, -1, vgx4], {z0.b-z3.b}, z0.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: usvdot za.s[w8, -1, vgx4], {z0.b-z3.b}, z0.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector select register
usvdot za.s[w7, 0, vgx4], {z4.b-z7.b}, z0.b[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: usvdot za.s[w7, 0, vgx4], {z4.b-z7.b}, z0.b[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usvdot za.s[w12, 0, vgx2], {z4.b-z5.b}, z0.b[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: usvdot za.s[w12, 0, vgx2], {z4.b-z5.b}, z0.b[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list
usvdot za.s[w8, 0, vgx4], {z0.b-z4.b}, z0.b[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: usvdot za.s[w8, 0, vgx4], {z0.b-z4.b}, z0.b[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
usvdot za.s[w8, 0, vgx4], {z1.b-z4.b}, z15.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: usvdot za.s[w8, 0, vgx4], {z1.b-z4.b}, z15.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Matrix Operand
usvdot za.h[w8, 0, vgx4], {z0.b-z3.b}, z4.b[7]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
// CHECK-NEXT: usvdot za.h[w8, 0, vgx4], {z0.b-z3.b}, z4.b[7]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector grouping
usvdot za.s[w8, 0, vgx2], {z0.b-z1.b}, z14.b[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: usvdot za.s[w8, 0, vgx2], {z0.b-z1.b}, z14.b[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid lane index
usvdot za.s[w8, 0, vgx4], {z0.b-z3.b}, z14.b[16]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]
// CHECK-NEXT: usvdot za.s[w8, 0, vgx4], {z0.b-z3.b}, z14.b[16]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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llvm/test/MC/AArch64/SME2/usvdot.s Normal file
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
usvdot za.s[w8, 0, vgx4], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10000000-00101000
// CHECK-INST: usvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
// CHECK-ENCODING: [0x28,0x80,0x50,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1508028 <unknown>
usvdot za.s[w8, 0], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10000000-00101000
// CHECK-INST: usvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
// CHECK-ENCODING: [0x28,0x80,0x50,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1508028 <unknown>
usvdot za.s[w10, 5, vgx4], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11000101-00101101
// CHECK-INST: usvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
// CHECK-ENCODING: [0x2d,0xc5,0x55,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c155c52d <unknown>
usvdot za.s[w10, 5], {z8.b - z11.b}, z5.b[1] // 11000001-01010101-11000101-00101101
// CHECK-INST: usvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]
// CHECK-ENCODING: [0x2d,0xc5,0x55,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c155c52d <unknown>
usvdot za.s[w11, 7, vgx4], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11101101-10101111
// CHECK-INST: usvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
// CHECK-ENCODING: [0xaf,0xed,0x58,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c158edaf <unknown>
usvdot za.s[w11, 7], {z12.b - z15.b}, z8.b[3] // 11000001-01011000-11101101-10101111
// CHECK-INST: usvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]
// CHECK-ENCODING: [0xaf,0xed,0x58,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c158edaf <unknown>
usvdot za.s[w11, 7, vgx4], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11101111-10101111
// CHECK-INST: usvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
// CHECK-ENCODING: [0xaf,0xef,0x5f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c15fefaf <unknown>
usvdot za.s[w11, 7], {z28.b - z31.b}, z15.b[3] // 11000001-01011111-11101111-10101111
// CHECK-INST: usvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]
// CHECK-ENCODING: [0xaf,0xef,0x5f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c15fefaf <unknown>
usvdot za.s[w8, 5, vgx4], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10001110-00101101
// CHECK-INST: usvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
// CHECK-ENCODING: [0x2d,0x8e,0x50,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1508e2d <unknown>
usvdot za.s[w8, 5], {z16.b - z19.b}, z0.b[3] // 11000001-01010000-10001110-00101101
// CHECK-INST: usvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]
// CHECK-ENCODING: [0x2d,0x8e,0x50,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1508e2d <unknown>
usvdot za.s[w8, 1, vgx4], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10000100-00101001
// CHECK-INST: usvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
// CHECK-ENCODING: [0x29,0x84,0x5e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c15e8429 <unknown>
usvdot za.s[w8, 1], {z0.b - z3.b}, z14.b[1] // 11000001-01011110-10000100-00101001
// CHECK-INST: usvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]
// CHECK-ENCODING: [0x29,0x84,0x5e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c15e8429 <unknown>
usvdot za.s[w10, 0, vgx4], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11000110-00101000
// CHECK-INST: usvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
// CHECK-ENCODING: [0x28,0xc6,0x54,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c154c628 <unknown>
usvdot za.s[w10, 0], {z16.b - z19.b}, z4.b[1] // 11000001-01010100-11000110-00101000
// CHECK-INST: usvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]
// CHECK-ENCODING: [0x28,0xc6,0x54,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c154c628 <unknown>
usvdot za.s[w8, 0, vgx4], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10001001-10101000
// CHECK-INST: usvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
// CHECK-ENCODING: [0xa8,0x89,0x52,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c15289a8 <unknown>
usvdot za.s[w8, 0], {z12.b - z15.b}, z2.b[2] // 11000001-01010010-10001001-10101000
// CHECK-INST: usvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]
// CHECK-ENCODING: [0xa8,0x89,0x52,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c15289a8 <unknown>
usvdot za.s[w10, 1, vgx4], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11001000-00101001
// CHECK-INST: usvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
// CHECK-ENCODING: [0x29,0xc8,0x5a,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c15ac829 <unknown>
usvdot za.s[w10, 1], {z0.b - z3.b}, z10.b[2] // 11000001-01011010-11001000-00101001
// CHECK-INST: usvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]
// CHECK-ENCODING: [0x29,0xc8,0x5a,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c15ac829 <unknown>
usvdot za.s[w8, 5, vgx4], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10001010-10101101
// CHECK-INST: usvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
// CHECK-ENCODING: [0xad,0x8a,0x5e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c15e8aad <unknown>
usvdot za.s[w8, 5], {z20.b - z23.b}, z14.b[2] // 11000001-01011110-10001010-10101101
// CHECK-INST: usvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]
// CHECK-ENCODING: [0xad,0x8a,0x5e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c15e8aad <unknown>
usvdot za.s[w11, 2, vgx4], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11100101-00101010
// CHECK-INST: usvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
// CHECK-ENCODING: [0x2a,0xe5,0x51,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c151e52a <unknown>
usvdot za.s[w11, 2], {z8.b - z11.b}, z1.b[1] // 11000001-01010001-11100101-00101010
// CHECK-INST: usvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]
// CHECK-ENCODING: [0x2a,0xe5,0x51,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c151e52a <unknown>
usvdot za.s[w9, 7, vgx4], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10101001-10101111
// CHECK-INST: usvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
// CHECK-ENCODING: [0xaf,0xa9,0x5b,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c15ba9af <unknown>
usvdot za.s[w9, 7], {z12.b - z15.b}, z11.b[2] // 11000001-01011011-10101001-10101111
// CHECK-INST: usvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]
// CHECK-ENCODING: [0xaf,0xa9,0x5b,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c15ba9af <unknown>