31 lines
580 B
Scala
31 lines
580 B
Scala
package projectname
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import spinal.core._
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// Hardware definition
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case class MyTopLevel() extends Component {
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val io = new Bundle {
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val cond0 = in Bool()
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val cond1 = in Bool()
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val flag = out Bool()
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val state = out UInt(8 bits)
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}
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val counter = Reg(UInt(8 bits)) init 0
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when(io.cond0) {
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counter := counter + 1
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}
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io.state := counter
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io.flag := (counter === 0) | io.cond1
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}
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object MyTopLevelVerilog extends App {
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Config.spinal.generateVerilog(MyTopLevel())
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}
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object MyTopLevelVhdl extends App {
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Config.spinal.generateVhdl(MyTopLevel())
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}
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