![]() onlyStdLogicVectorAtTopLevelIo = false as it prevent VHDL / GHDL sim |
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.. | ||
Config.scala | ||
MyTopLevel.scala | ||
MyTopLevelFormal.scala | ||
MyTopLevelSim.scala |
![]() onlyStdLogicVectorAtTopLevelIo = false as it prevent VHDL / GHDL sim |
||
---|---|---|
.. | ||
Config.scala | ||
MyTopLevel.scala | ||
MyTopLevelFormal.scala | ||
MyTopLevelSim.scala |