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SpinalTemplateSbt
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SpinalTemplateSbt/hw
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Dolu1990 976ceca3a3
Update Config.scala 
onlyStdLogicVectorAtTopLevelIo = false as it prevent VHDL / GHDL sim
 		2025-04-06 14:58:20 +02:00
..
gen refactor: simplify project structure 2022-11-25 10:39:48 +01:00
spinal/projectname Update Config.scala 2025-04-06 14:58:20 +02:00
verilog refactor: simplify project structure 2022-11-25 10:39:48 +01:00
vhdl refactor: simplify project structure 2022-11-25 10:39:48 +01:00