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llvm-project/llvm/test/CodeGen/RISCV
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Anton Sidorenko 14a5b9cdae [MachineCombiner][RISCV] Relax optimization level requirement 
Enable Machine Combiner for O1/O2/O3 optimization levels. It makes RISCV
consistent with other targets running Machine Combiner.

Originally it was enabled only for -O3, however I looked through time reports
and usually it takes 0.1%-0.4% of total time, and never takes more than 1.0%.

Differential Revision: https://reviews.llvm.org/D136339
 		2022-10-21 13:25:28 +03:00
..
GlobalISel [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
intrinsics
…
rvv [MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with scalable vector stack id. 2022-10-20 14:05:46 -07:00
MachineSink-implicit-x0.mir Fix minor deficiency in machine-sink. 2021-11-12 08:01:13 +01:00
O0-pipeline.ll Fix remaining test failures for "[llvm/CodeGen] Enable the ExpandLargeDivRem pass for X86, Arm and AArch64" 2022-09-06 16:38:43 +01:00
O3-pipeline.ll [MachineCombiner][RISCV] Enable MachineCombiner for RISCV 2022-10-18 18:56:32 +03:00
add-before-shl.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
add-imm.ll [RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]). 2022-06-24 08:31:52 -07:00
addc-adde-sube-subc.ll
…
addcarry.ll [test][DAGCombine] Add more tests for carry diamond. NFC 2022-01-27 00:25:26 +01:00
addimm-mulimm.ll [RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]). 2022-06-24 08:31:52 -07:00
addrspacecast.ll
…
aext-to-sext.ll [RISCV] Add signext attribute to i32 arguments in some tests. NFC 2022-10-08 10:50:16 -07:00
align-loops.ll [CodeGen] Add -align-loops 2021-08-04 12:45:18 -07:00
align.ll
…
alloca.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
alu8.ll [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount. 2022-07-14 16:10:14 -07:00
alu16.ll [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount. 2022-07-14 16:10:14 -07:00
alu32.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
alu64.ll [RISCV] Use branchless form for selects with 0 in either arm 2022-10-12 13:51:52 -07:00
analyze-branch.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
and.ll [RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and some trailing zeros. 2022-08-30 12:22:46 -07:00
arith-with-overflow.ll
…
atomic-cmpxchg-branch-on-result.ll [RISCV] Avoid redundant branch-to-branch when expanding cmpxchg 2022-08-17 13:49:15 +01:00
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
atomic-fence.ll
…
atomic-load-store.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
atomic-rmw.ll [SDAG] try to replace subtract-from-constant with xor 2022-07-08 08:14:24 -04:00
atomic-signext.ll [RISCV] Teach ComputeNumSignBitsForTargetNode about masked atomic intrinsics 2022-08-03 13:41:58 +01:00
attributes.ll [RISCV] Remove support for the unratified Zbe, Zbf, and Zbm extensions. 2022-09-22 13:04:41 -07:00
bitreverse-shift.ll [RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases 2022-03-30 11:46:42 -07:00
bittest.ll [RISCV] Use branchless form for selects with 0 in either arm 2022-10-12 13:51:52 -07:00
blockaddress.ll
…
branch-relaxation.ll [RISCV][test] Update branch-relaxation.ll with update_llc_test_checks.py [NFC] 2022-08-25 17:01:34 +08:00
branch.ll
…
bswap-bitreverse.ll [RISCV] Remove support for the unratified Zbp extension. 2022-09-21 21:22:42 -07:00
bswap-shift.ll [RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases 2022-03-30 11:46:42 -07:00
byval.ll [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
callee-saved-fpr32s.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
callee-saved-fpr64s.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
callee-saved-gprs.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
calling-conv-half.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
calling-conv-ilp32-ilp32f-common.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
calling-conv-ilp32.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
calling-conv-ilp32d.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
calling-conv-ilp32f-ilp32d-common.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
calling-conv-lp64-lp64f-common.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
calling-conv-lp64-lp64f-lp64d-common.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
calling-conv-lp64.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
calling-conv-rv32f-ilp32.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
calling-conv-sext-zext.ll
…
calling-conv-vector-float.ll [RISCV] Fix a crash when lowering split float arguments 2021-07-22 09:55:26 +01:00
calls.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
cmp-bool.ll
…
codemodel-lowering.ll [RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI 2022-08-01 11:30:02 +02:00
compress-float.ll [NFC][llvm] Inclusive language: reword uses of sanity test and check 2021-11-25 07:21:42 -05:00
compress-inline-asm.ll
…
compress-opt-branch.ll [RISCV] Optimization for using compressed beqz and bnez PR#56391 2022-10-06 09:33:32 -07:00
compress-opt-select.ll [RISCV] Use branchless form for selects with 0 in either arm 2022-10-12 13:51:52 -07:00
compress.ll [NFC][llvm] Inclusive language: reword uses of sanity test and check 2021-11-25 07:21:42 -05:00
copy-frameindex.mir llvm-reduce: Don't assert on functions which don't track liveness 2022-06-07 10:00:25 -04:00
copysign-casts.ll [RISCV] Select (srl (and X, C2) as (slli (srliw X, C3), C3-C). 2022-06-29 09:15:09 -07:00
ctlz-cttz-ctpop.ll [RISCV] Optimize SELECT_CC when the true value of select is Constant 2022-10-18 09:24:17 +08:00
disable-tail-calls.ll
…
disjoint.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
div-by-constant.ll [LegalizeTypes] Improve splitting for urem/udiv by constant for some constants. 2022-09-12 10:34:52 -07:00
div-pow2.ll [RISCV] Remove support for the unratified Zbt extension. 2022-09-20 20:26:48 -07:00
div.ll [LegalizeTypes] Improve splitting for urem/udiv by constant for some constants. 2022-09-12 10:34:52 -07:00
div_minsize.ll [RISCV]Enable isIntDivCheap when attribute is minsize 2022-07-27 18:22:51 +08:00
double-arith-strict.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
double-arith.ll [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u 2022-07-13 19:37:34 +01:00
double-bitmanip-dagcombines.ll [RISCV] Select SRLI+SLLI for AND with leading ones mask 2022-03-16 02:10:57 +00:00
double-br-fcmp.ll [RISCV] Restore "Enable shrink wrap by default" 2022-07-02 11:13:13 +08:00
double-calling-conv.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
double-convert-strict.ll [RISCV] Optimize SELECT_CC when the true value of select is Constant 2022-10-18 09:24:17 +08:00
double-convert.ll [RISCV] Optimize SELECT_CC when the true value of select is Constant 2022-10-18 09:24:17 +08:00
double-fcmp-strict.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
double-fcmp.ll [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u 2022-07-13 19:37:34 +01:00
double-frem.ll [RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls 2022-08-10 10:50:29 +01:00
double-imm.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
double-intrinsics-strict.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
double-intrinsics.ll [RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls 2022-08-10 10:50:29 +01:00
double-isnan.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
double-mem.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
double-previous-failure.ll [RISCV] Teach combineDeMorganOfBoolean to handle (and (xor X, 1), (not Y)). 2022-08-25 10:55:45 -07:00
double-round-conv-sat.ll [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect 2022-10-13 09:06:12 -07:00
double-round-conv.ll [RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls 2022-08-10 10:50:29 +01:00
double-select-fcmp.ll [RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1). 2022-08-17 09:50:08 -07:00
double-select-icmp.ll [RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC 2022-08-16 21:28:26 -07:00
double-stack-spill-restore.ll [RISCV] Restore "Enable shrink wrap by default" 2022-07-02 11:13:13 +08:00
dwarf-eh.ll
…
early-clobber-tied-def-subreg-liveness.ll [RISCV][InsertVSETVLI] Default to MA not MU 2022-10-06 07:59:39 -07:00
early-clobber-tied-def-subreg-liveness.mir Reland "[SplitKit] Handle early clobber + tied to def correctly" 2022-06-16 17:13:09 +08:00
eh-dwarf-cfa.ll [RISCV] Add ISD::EH_DWARF_CFA 2022-06-08 22:03:30 +08:00
elf-preemption.ll [RISCV] Pre-RA expand pseudos pass 2022-07-31 23:19:00 +02:00
exception-pointer-register.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
fastcc-float.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
fastcc-int.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
fixups-diff.ll
…
fixups-relax-diff.ll
…
float-arith-strict.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
float-arith.ll [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u 2022-07-13 19:37:34 +01:00
float-bit-preserving-dagcombines.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
float-bitmanip-dagcombines.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
float-br-fcmp.ll [RISCV] Restore "Enable shrink wrap by default" 2022-07-02 11:13:13 +08:00
float-convert-strict.ll [RISCV] Optimize SELECT_CC when the true value of select is Constant 2022-10-18 09:24:17 +08:00
float-convert.ll [RISCV] Optimize SELECT_CC when the true value of select is Constant 2022-10-18 09:24:17 +08:00
float-fcmp-strict.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
float-fcmp.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
float-frem.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
float-imm.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
float-intrinsics-strict.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
float-intrinsics.ll [RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls 2022-08-10 10:50:29 +01:00
float-isnan.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
float-mem.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
float-round-conv-sat.ll [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect 2022-10-13 09:06:12 -07:00
float-round-conv.ll [RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls 2022-08-10 10:50:29 +01:00
float-select-fcmp.ll [RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1). 2022-08-17 09:50:08 -07:00
float-select-icmp.ll [RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC 2022-08-16 21:28:26 -07:00
flt-rounds.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
fmax-fmin.ll [SDAG] avoid libcalls to fmin/fmax for soft-float targets 2022-03-30 11:22:03 -04:00
fold-addi-loadstore.ll [RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI 2022-08-01 11:30:02 +02:00
fold-vector-cmp.ll [RISCV][InsertVSETVLI] Default to MA not MU 2022-10-06 07:59:39 -07:00
forced-atomics.ll [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect 2022-10-13 09:06:12 -07:00
fp-imm.ll [RISCV] Optimize lowering of floating-point -0.0 2022-01-20 11:46:28 +00:00
fp16-promote.ll [RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls 2022-08-10 10:50:29 +01:00
fp128.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
fpclamptosat.ll [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect 2022-10-13 09:06:12 -07:00
fpclamptosat_vec.ll [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect 2022-10-13 09:06:12 -07:00
fpenv.ll
…
frame-info.ll [RISCV] Restore "Enable shrink wrap by default" 2022-07-02 11:13:13 +08:00
frame.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
frameaddr-returnaddr.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
frm-dependency.ll [RISCV] Update some tests to use floating point ABI where it makes sense. 2022-02-24 09:27:57 -08:00
get-register-invalid.ll
…
get-register-noreserve.ll [RISCV] Add llvm.read.register support for vlenb 2022-05-13 09:12:02 -07:00
get-register-reserve.ll
…
get-setcc-result-type.ll Recommit "[RISCV] Use setcc's original SDLoc when inverting it in performSUBCombine." 2022-08-16 15:51:07 -07:00
ghccc-rv32.ll
…
ghccc-rv64.ll
…
global-merge-offset.ll [RISCV] Add the GlobalMerge pass (disabled by default) 2022-09-08 18:40:38 -07:00
global-merge.ll [RISCV] Add the GlobalMerge pass (disabled by default) 2022-09-08 18:40:38 -07:00
half-arith-strict.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
half-arith.ll [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u 2022-07-13 19:37:34 +01:00
half-bitmanip-dagcombines.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-br-fcmp.ll [RISCV] Restore "Enable shrink wrap by default" 2022-07-02 11:13:13 +08:00
half-convert-strict.ll [RISCV] Optimize SELECT_CC when the true value of select is Constant 2022-10-18 09:24:17 +08:00
half-convert.ll [RISCV] Optimize SELECT_CC when the true value of select is Constant 2022-10-18 09:24:17 +08:00
half-fcmp-strict.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
half-fcmp.ll [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u 2022-07-13 19:37:34 +01:00
half-frem.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-imm.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
half-intrinsics.ll [RISCV] Simplify check-prefixes in half-intrinsics.ll. NFC 2022-09-23 13:26:07 -07:00
half-isnan.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
half-mem.ll [RISCV] Use check-prefixes to reduce check lines 2022-06-06 15:59:15 +08:00
half-round-conv-sat.ll [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect 2022-10-13 09:06:12 -07:00
half-round-conv.ll [RISCV] Add codegen coverage for ceil/floor/trunc/round/roundeven within FPR 2022-07-26 08:48:46 -07:00
half-select-fcmp.ll [RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1). 2022-08-17 09:50:08 -07:00
half-select-icmp.ll [RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC 2022-08-16 21:28:26 -07:00
hoist-global-addr-base.ll [RISCV] Simplify test case from D130931. NFC 2022-08-01 16:50:56 -07:00
hwasan-check-memaccess.ll [RISC-V][HWASAN] Add support for lowering HWASAN intrinsic for RISC-V 2022-08-28 21:22:13 +03:00
i32-icmp.ll [RISCV] Use SLTIU X, -1 for (setne X, -1). 2022-08-11 15:36:04 -07:00
i64-icmp.ll [RISCV] Use SLTIU X, -1 for (setne X, -1). 2022-08-11 15:36:04 -07:00
iabs.ll [RISCV] Remove support for the unratified Zbt extension. 2022-09-20 20:26:48 -07:00
imm-cse.ll
…
imm.ll [RISCV] Improve constant materialization for cases that can use LUI+ADDI instead of LUI+ADDIW. 2022-04-29 08:58:32 -07:00
indirectbr.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
init-array.ll
…
inline-asm-S-constraint.ll [RISCV] Support machine constraint "S" 2021-07-13 09:30:09 -07:00
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll [RISCV] Update computeTargetABI from llc as well as clang 2022-02-24 21:55:44 -08:00
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll [RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint. 2022-03-02 11:22:46 -08:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll [RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint. 2022-03-02 11:22:46 -08:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll [RISCV] Don't allow vector types to be used with inline asm 'r' constraint 2021-12-23 20:32:36 -06:00
inline-asm-zfh-constraint-f.ll [RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint. 2022-03-02 11:22:46 -08:00
inline-asm.ll [RISCV] Don't advertise i32->i64 zextload as free for RV64. 2022-01-06 08:13:42 -08:00
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
interrupt-attr-ret-error.ll
…
interrupt-attr.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
isel-optnone.ll [RISCV] Pass OptLevel to `RISCVDAGToDAGISel` correctly 2022-05-30 17:22:50 -07:00
jumptable.ll [RISCV] Pre-RA expand pseudos pass 2022-07-31 23:19:00 +02:00
large-stack.ll [RISCV] Merge addi into load/store as there is a ADD between them 2022-04-29 04:33:05 +00:00
legalize-fneg.ll [RISCV] Teach targetShrinkDemandedConstant to handle OR and XOR. 2022-07-17 12:36:33 -07:00
libcall-tail-calls.ll [RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls 2022-08-10 10:50:29 +01:00
lit.local.cfg
…
live-sp.mir [RISCV] Fix invalid kill on callee save 2021-11-02 11:56:54 +00:00
local-stack-slot-allocation.ll [RISCV] Enable the LocalStackSlotAllocation pass support 2022-10-19 16:15:14 +08:00
loop-strength-reduce-add-cheaper-than-mul.ll [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. 2022-05-27 11:05:18 -07:00
loop-strength-reduce-loop-invar.ll [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. 2022-05-27 11:05:18 -07:00
lsr-legaladdimm.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
machine-combiner-mir.ll [MachineCombiner][RISCV] Relax optimization level requirement 2022-10-21 13:25:28 +03:00
machine-combiner.ll [MachineCombiner][RISCV] Relax optimization level requirement 2022-10-21 13:25:28 +03:00
machine-cp.mir [MachineCopyPropagation][RISCV] Fix D125335 accidentally change control flow. 2022-06-17 21:40:08 -07:00
machine-cse.ll [RISCV] Add isCommutable to FADD/FMUL/FMIN/FMAX/FEQ. 2022-05-02 20:21:16 -07:00
machine-outliner-cfi.mir [RISCV] Precommit test for D122634 2022-04-22 12:19:55 +08:00
machine-outliner-patchable.ll [MachineOutliner] Don't outline functions starting with PATCHABLE_FUNCTION_ENTER/FENTRL_CALL 2021-12-13 13:24:29 -08:00
machine-outliner-position.mir [RISCV] Precommit test for D122634 2022-04-22 12:19:55 +08:00
machine-outliner-throw.ll [RISCV] Do not outline CFI instructions when they are needed in EH 2022-04-22 12:28:19 +08:00
machinelicm-address-pseudos.ll [RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI 2022-08-01 11:30:02 +02:00
machineoutliner-jumptable.mir [RISCV] Fix Machine Outliner jump table handling. 2021-09-09 07:32:30 +02:00
machineoutliner-pcrel-lo.mir [RISCV] Don't outline pcrel-lo operand. 2022-08-24 21:47:46 +08:00
machineoutliner.mir
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macro-fusion-lui-addi.ll [RISCV] Add macrofusion infrastructure and one example usage. 2022-06-23 08:38:39 -07:00
make-compressible-for-store-address.mir [RISCV] Fix wrong register rename for store value during make-compressible optimization 2022-07-08 18:07:17 +08:00
make-compressible-rv64.mir [RISCV] Add pre-emit pass to make more instructions compressible 2022-05-25 09:25:02 +01:00
make-compressible.mir [RISCV] Add pre-emit pass to make more instructions compressible 2022-05-25 09:25:02 +01:00
mattr-invalid-combination.ll [RISCV] Remove check and update test file in D121183 2022-03-24 00:48:52 +08:00
mem.ll [RISCV] Add tests for (load (add X, [2048,4094])). NFC 2022-06-27 13:42:57 -07:00
mem64.ll [RISCV] Make custom isel for (add X, imm) used by load/stores more selective. 2022-06-30 14:20:11 -07:00
memcpy-inline.ll [RISCV] Teach shouldConvertConstantLoadToIntImm that constant materialization can use constant pools. 2022-07-10 14:10:17 -07:00
min-max.ll [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect 2022-10-13 09:06:12 -07:00
mir-target-flags.ll [RISCV] Pre-RA expand pseudos pass 2022-07-31 23:19:00 +02:00
miss-sp-restore-eh.ll [RISCV] Fix missing stack pointer recover 2022-06-09 23:38:50 +08:00
module-target-abi.ll
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module-target-abi2.ll [RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute 2022-03-24 00:48:52 +08:00
module-target-abi3.ll [RISCV] Generate correct ELF abi flag when empty .ll file has target-abi attribute 2022-08-26 14:39:39 +08:00
mul.ll Revert "[DAGCombiner] Fold (mul (sra X, BW-1), Y) -> (neg (and (sra X, BW-1), Y))" 2022-10-11 16:30:40 -07:00
musttail-call.ll
…
narrow-shl-cst.ll [RISCV] Reorder (and/or/xor (shl X, C1), C2) if we can form ANDI/ORI/XORI. 2022-07-27 17:35:26 -07:00
neg-abs.ll [RISCV] Remove support for the unratified Zbt extension. 2022-09-20 20:26:48 -07:00
nomerge.ll
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option-nopic.ll
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option-norelax.ll
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option-norvc.ll
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option-pic.ll
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option-relax.ll
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option-rvc.ll
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optnone-store-no-combine.ll [DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience 2021-12-23 10:48:28 +05:30
out-of-reach-emergency-slot.mir [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
overflow-intrinsic-optimizations.ll [RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3() 2021-08-31 11:23:56 -07:00
patchable-function-entry.ll
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pic-models.ll [RISCV] Pre-RA expand pseudos pass 2022-07-31 23:19:00 +02:00
pr40333.ll
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pr51206.ll [RISCV] Use MULHU for more division by constant cases. 2021-12-09 09:10:14 -08:00
pr53662.mir [RISCV] Don't getDebugLoc for the end node of MBB iterator 2022-04-30 16:00:20 +08:00
pr55201.ll [DAGCombiner] When matching a disguised rotate by constant don't forget to apply LHSMask/RHSMask. 2022-04-30 11:02:30 -07:00
pr56110.ll [DAGCombiner][ARM][RISCV] Teach ShrinkLoadReplaceStoreWithStore to use truncstore. 2022-06-19 15:50:15 -07:00
pr56457.ll [TargetLowering][RISCV] Make expandCTLZ work for non-power of 2 types. 2022-07-12 11:36:37 -07:00
pr58025.ll [RISCV][SelectionDAGBuilder] Fix crash when copying a v1f32 vector between basic blocks. 2022-09-28 10:13:35 -07:00
prefetch.ll [IR] Update llvm.prefetch to match docs 2022-08-19 09:11:17 +01:00
readcyclecounter.ll
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regalloc-last-chance-recoloring-failure.ll [RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand. 2022-10-11 16:40:16 -07:00
rem.ll [RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls 2022-08-10 10:50:29 +01:00
remat.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
reserved-reg-errors.ll
…
reserved-regs.ll
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riscv-codegenprepare-asm.ll [RISCV] Teach RISCVCodeGenPrepare to optimize (i64 (and (zext/sext (i32 X), C1))) 2022-07-17 11:00:56 -07:00
riscv-codegenprepare.ll [RISCV] Teach RISCVCodeGenPrepare to optimize (i64 (and (zext/sext (i32 X), C1))) 2022-07-17 11:00:56 -07:00
rotl-rotr.ll [RISCV] Use branchless form for selects with 0 in either arm 2022-10-12 13:51:52 -07:00
rv32e.ll
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rv32i-rv64i-float-double.ll [NFC][llvm] Inclusive language: reword uses of sanity test and check 2021-11-25 07:21:42 -05:00
rv32i-rv64i-half.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
rv32zba.ll [RISCV] Don't use li+sh3add for constants that can use lui+add. 2022-08-05 12:47:03 -07:00
rv32zbb-intrinsic.ll [RISCV] Add computeKnownBits support for RISCVISD::GORC. 2022-03-28 16:56:33 -07:00
rv32zbb-zbkb.ll [RISCV] Use branchless form for selects with 0 in either arm 2022-10-12 13:51:52 -07:00
rv32zbb.ll [RISCV] Optimize SELECT_CC when the true value of select is Constant 2022-10-18 09:24:17 +08:00
rv32zbc-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv32zbc-zbkc-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv32zbkb-intrinsic.ll [RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV. 2022-01-30 12:41:09 -08:00
rv32zbkb.ll [RISCV] Remove support for the unratified Zbp extension. 2022-09-21 21:22:42 -07:00
rv32zbkx-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv32zbs.ll [RISCV] Use branchless form for selects with 0 in either arm 2022-10-12 13:51:52 -07:00
rv32zknd-intrinsic.ll [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u 2022-07-13 19:37:34 +01:00
rv32zkne-intrinsic.ll [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u 2022-07-13 19:37:34 +01:00
rv32zknh-intrinsic.ll [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u 2022-07-13 19:37:34 +01:00
rv32zksed-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zksh-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64-large-stack.ll [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants. 2021-07-20 09:22:06 -07:00
rv64d-double-convert-strict.ll [RISCV] Update some tests to use floating point ABI where it makes sense. 2022-02-24 09:27:57 -08:00
rv64d-double-convert.ll [RISCV] Update some tests to use floating point ABI where it makes sense. 2022-02-24 09:27:57 -08:00
rv64f-float-convert-strict.ll [RISCV] Set target-abi explicitly to reduce codegen results 2022-06-01 13:49:23 +08:00
rv64f-float-convert.ll [RISCV] Set target-abi explicitly to reduce codegen results 2022-06-01 13:49:23 +08:00
rv64i-complex-float.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
rv64i-demanded-bits.ll [RISCV] Use hasAllWUsers to recover XORI/ORI 2022-10-10 14:16:50 +08:00
rv64i-double-softfloat.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
rv64i-exhaustive-w-insts.ll [RISCV][NFC] Remove solved TODO for combining constant shifts 2022-05-26 09:55:19 +08:00
rv64i-shift-sext.ll [RISCV] Relax another one use restriction in performSRACombine. 2022-08-04 14:32:31 -07:00
rv64i-single-softfloat.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
rv64m-exhaustive-w-insts.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
rv64m-w-insts-legalization.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
rv64zba.ll [RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and some trailing zeros. 2022-08-30 12:22:46 -07:00
rv64zbb-intrinsic.ll [RISCV] Remove support for the unratified Zbp extension. 2022-09-21 21:22:42 -07:00
rv64zbb-zbkb.ll [RISCV] Remove support for the unratified Zbp extension. 2022-09-21 21:22:42 -07:00
rv64zbb.ll [TargetLowering][RISCV][Sparc] Don't emit zero check in CTTZTableLookup for CTTZ_ZERO_UNDEF. 2022-10-17 10:15:39 -07:00
rv64zbc-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv64zbc-zbkc-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv64zbkb-intrinsic.ll [RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV. 2022-01-30 12:41:09 -08:00
rv64zbkb.ll [RISCV] Remove support for the unratified Zbp extension. 2022-09-21 21:22:42 -07:00
rv64zbkx-intrinsic.ll [RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC 2022-03-01 11:37:49 -08:00
rv64zbs.ll [RISCV] Recognize bexti from (srl (and X, 1<<C), C). 2022-07-20 15:03:52 -07:00
rv64zfh-half-convert-strict.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
rv64zfh-half-convert.ll [RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X). 2022-02-24 09:19:01 -08:00
rv64zfh-half-intrinsics.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
rv64zknd-intrinsic.ll [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u 2022-07-13 19:37:34 +01:00
rv64zknd-zkne-intrinsic.ll [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u 2022-07-13 19:37:34 +01:00
rv64zkne-intrinsic.ll [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u 2022-07-13 19:37:34 +01:00
rv64zknh-intrinsic.ll [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u 2022-07-13 19:37:34 +01:00
rv64zksed-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zksh-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
sadd_sat.ll [RISCV] Remove support for the unratified Zbt extension. 2022-09-20 20:26:48 -07:00
sadd_sat_plus.ll [RISCV] Remove support for the unratified Zbt extension. 2022-09-20 20:26:48 -07:00
saverestore.ll
…
scalable-vector-struct.ll [RISCV] Remove experimental prefix from rvv-related extensions. 2022-01-22 20:18:40 -08:00
sdata-limit-0.ll
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sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
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select-and.ll [RISCV] Remove support for the unratified Zbt extension. 2022-09-20 20:26:48 -07:00
select-bare.ll [RISCV] Remove support for the unratified Zbt extension. 2022-09-20 20:26:48 -07:00
select-binop-identity.ll [RISCV] Generalize select (and (x , 0x1) == 0), y, (z ^ y) ) and select (and (x , 0x1) == 0), y, (z | y) ) transforms by removing and-clause 2022-10-03 13:57:38 -07:00
select-cc.ll [RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments. 2022-10-04 15:39:10 -07:00
select-const.ll [RISCV] Remove support for the unratified Zbt extension. 2022-09-20 20:26:48 -07:00
select-constant-xor.ll [RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range 2022-03-29 14:46:49 +08:00
select-optimize-multiple.ll [RISCV] Remove support for the unratified Zbt extension. 2022-09-20 20:26:48 -07:00
select-optimize-multiple.mir [RISCV] Remove support for the unratified Zbt extension. 2022-09-20 20:26:48 -07:00
select-or.ll [RISCV] Remove support for the unratified Zbt extension. 2022-09-20 20:26:48 -07:00
select.ll [RISCV] Branchless lowering for select (and (x , 0x1) == 0), y, (z ^ y) ) and select (and (x , 0x1) == 0), y, (z | y) ) 2022-09-30 08:24:32 -07:00
selectcc-to-shiftand.ll [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect 2022-10-13 09:06:12 -07:00
setcc-logic.ll [RISCV] Add signext attribute to i32 arguments in some tests. NFC 2022-10-08 10:50:16 -07:00
sext-zext-trunc.ll [RISCV] Remove C!=0 restriction from (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq)). 2022-08-16 14:49:52 -07:00
sextw-removal.ll [RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments. 2022-10-04 15:39:10 -07:00
shadowcallstack.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
shift-and.ll [RISCV] Add another isel optimization for (and (shl x, c2), c1) 2021-09-23 14:18:07 -07:00
shift-masked-shamt.ll [RISCV] Use branchless form for selects with 0 in either arm 2022-10-12 13:51:52 -07:00
shifts.ll [RISCV] Use branchless form for selects with 0 in either arm 2022-10-12 13:51:52 -07:00
shl-demanded.ll [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount. 2022-07-14 16:10:14 -07:00
shlimm-addimm.ll [RISCV][test] Add tests of (add (shl r, c0), c1) 2021-10-14 14:53:03 +00:00
short-foward-branch-opt.ll [RISCV] Add basic support for the sifive-7-series short forward branch optimization. 2022-10-17 13:56:22 -07:00
shrinkwrap.ll [RISCV] Restore "Enable shrink wrap by default" 2022-07-02 11:13:13 +08:00
shuffle-reverse.ll [RISCV][InsertVSETVLI] Default to MA not MU 2022-10-06 07:59:39 -07:00
sink-icmp.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
spill-fpr-scalar.ll [RISCV][InsertVSETVLI] Default to MA not MU 2022-10-06 07:59:39 -07:00
split-offsets.ll [RISCV] Modify the custom isel for (add X, imm) used by load/stores. 2022-07-09 22:47:27 -07:00
split-sp-adjust.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
split-udiv-by-constant.ll Revert "[TargetLowering][RISCV][X86] Support even divisors in expandDIVREMByConstant." 2022-10-10 14:53:29 -07:00
split-urem-by-constant.ll Revert "[TargetLowering][RISCV][X86] Support even divisors in expandDIVREMByConstant." 2022-10-10 14:53:29 -07:00
srem-lkk.ll [RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls 2022-08-10 10:50:29 +01:00
srem-seteq-illegal-types.ll [RISCV][InsertVSETVLI] Default to MA not MU 2022-10-06 07:59:39 -07:00
srem-vector-lkk.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
ssub_sat.ll [RISCV] Remove support for the unratified Zbt extension. 2022-09-20 20:26:48 -07:00
ssub_sat_plus.ll [RISCV] Remove support for the unratified Zbt extension. 2022-09-20 20:26:48 -07:00
stack-folding.ll [RISCV] Add sext.b/h and zext.b/h/w to RISCVInstrInfo::foldMemoryOperandImpl. 2022-07-21 14:54:58 -07:00
stack-realignment-with-variable-sized-objects.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
stack-realignment.ll [RISCV] Use two ADDIs to do some stack pointer adjustments. 2022-05-31 10:25:28 -07:00
stack-slot-size.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
stack-store-check.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
subtarget-features-std-ext.ll
…
switch-width.ll [riscv] Add a bunch of tests exploring switch lowering 2022-05-11 13:16:31 -07:00
tail-calls.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
target-abi-invalid.ll
…
target-abi-valid.ll
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thread-pointer.ll
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tls-models.ll [RISCV] Pre-RA expand pseudos pass 2022-07-31 23:19:00 +02:00
trunc-free.ll [RISCV] Enable isTruncateFree in SDAG for i64->i32 on rv64. 2022-08-15 08:32:51 -07:00
uadd_sat.ll [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect 2022-10-13 09:06:12 -07:00
uadd_sat_plus.ll [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect 2022-10-13 09:06:12 -07:00
umulo-128-legalisation-lowering.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
unaligned-load-store.ll [RISCV] Add a subtarget feature to enable unaligned scalar loads and stores 2022-05-26 15:25:47 -07:00
unfold-masked-merge-scalar-variablemask.ll [RISCV][NFC] Reorganize check prefixes in some tests to reduce redundant lines 2022-04-13 10:01:07 +00:00
unroll-loop-cse.ll Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove" 2022-02-17 17:27:37 +08:00
urem-lkk.ll [RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls 2022-08-10 10:50:29 +01:00
urem-seteq-illegal-types.ll [RISCV][InsertVSETVLI] Default to MA not MU 2022-10-06 07:59:39 -07:00
urem-vector-lkk.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
usub_sat.ll [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect 2022-10-13 09:06:12 -07:00
usub_sat_plus.ll [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect 2022-10-13 09:06:12 -07:00
vadd-vp-mask.ll [RISCV][InsertVSETVLI] Default to MA not MU 2022-10-06 07:59:39 -07:00
vararg.ll [RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and some trailing zeros. 2022-08-30 12:22:46 -07:00
vec3-setcc-crash.ll [RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect 2022-10-13 09:06:12 -07:00
vector-abi.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
verify-instr.mir
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vlenb.ll Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV) 2022-05-16 16:38:30 -07:00
vmul-vp-mask.ll [RISCV][InsertVSETVLI] Default to MA not MU 2022-10-06 07:59:39 -07:00
vsub-vp-mask.ll [RISCV][InsertVSETVLI] Default to MA not MU 2022-10-06 07:59:39 -07:00
wide-mem.ll
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xaluo.ll Revert "[DAGCombiner] Fold (mul (sra X, BW-1), Y) -> (neg (and (sra X, BW-1), Y))" 2022-10-11 16:30:40 -07:00
zext-with-load-is-free.ll [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering. 2022-05-27 11:05:18 -07:00
zfh-half-intrinsics-strict.ll [LegalizeTypes][RISCV] Support f16 in ExpandIntRes_LLROUND_LLRINT. 2022-09-26 11:09:33 -07:00
zfh-half-intrinsics.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
zfh-imm.ll [RISCV] Optimize lowering of floating-point -0.0 2022-01-20 11:46:28 +00:00
zmmul.ll [RISCV][Clang] Add support for Zmmul extension 2022-07-18 20:26:08 -04:00