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[RISCV] Teach ComputeNumSignBitsForTargetNode about masked atomic intrinsics 

An unnecessary sext.w is generated when masking the result of the
riscv_masked_cmpxchg_i64 intrinsic. Implementing handling of the
intrinsic in ComputeNumSignBitsForTargetNode allows it to be removed.

Although this isn't a particularly important optimisation, removing the
sext.w simplifies implementation of an additional cmpxchg-related
optimisation in D130192.

Although I can't produce a test with different codegen for the other
atomics intrinsics, these are added as well for completeness.

Differential Revision: https://reviews.llvm.org/D130191
This commit is contained in:
Alex Bradbury 2022-08-03 13:41:58 +01:00
parent d4cab87094
commit 28f12a09ae
3 changed files with 25 additions and 4 deletions
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25
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -9882,6 +9882,31 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
return XLen - EltBits + 1;
break;
}
case ISD::INTRINSIC_W_CHAIN: {
unsigned IntNo = Op.getConstantOperandVal(1);
switch (IntNo) {
default:
break;
case Intrinsic::riscv_masked_atomicrmw_xchg_i64:
case Intrinsic::riscv_masked_atomicrmw_add_i64:
case Intrinsic::riscv_masked_atomicrmw_sub_i64:
case Intrinsic::riscv_masked_atomicrmw_nand_i64:
case Intrinsic::riscv_masked_atomicrmw_max_i64:
case Intrinsic::riscv_masked_atomicrmw_min_i64:
case Intrinsic::riscv_masked_atomicrmw_umax_i64:
case Intrinsic::riscv_masked_atomicrmw_umin_i64:
case Intrinsic::riscv_masked_cmpxchg_i64:
// riscv_masked_{atomicrmw_*,cmpxchg} intrinsics represent an emulated
// narrow atomic operation. These are implemented using atomic
// operations at the minimum supported atomicrmw/cmpxchg width whose
// result is then sign extended to XLEN. With +A, the minimum width is
// 32 for both 64 and 32.
assert(Subtarget.getXLen() == 64);
assert(getMinCmpXchgSizeInBits() == 32);
assert(Subtarget.hasStdExtA());
return 33;
}
}
}
return 1;

2
llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
View File

@ -130,7 +130,6 @@ define void @cmpxchg_masked_and_branch1(i8* %ptr, i8 signext %cmp, i8 signext %v
; RV64IA-NEXT: .LBB2_5: # %do_cmpxchg
; RV64IA-NEXT: # in Loop: Header=BB2_1 Depth=1
; RV64IA-NEXT: and a4, a4, a0
; RV64IA-NEXT: sext.w a4, a4
; RV64IA-NEXT: bne a1, a4, .LBB2_1
; RV64IA-NEXT: # %bb.2: # %exit
; RV64IA-NEXT: ret
@ -207,7 +206,6 @@ define void @cmpxchg_masked_and_branch2(i8* %ptr, i8 signext %cmp, i8 signext %v
; RV64IA-NEXT: .LBB3_5: # %do_cmpxchg
; RV64IA-NEXT: # in Loop: Header=BB3_1 Depth=1
; RV64IA-NEXT: and a4, a4, a0
; RV64IA-NEXT: sext.w a4, a4
; RV64IA-NEXT: beq a1, a4, .LBB3_1
; RV64IA-NEXT: # %bb.2: # %exit
; RV64IA-NEXT: ret

2
llvm/test/CodeGen/RISCV/atomic-signext.ll
View File

@ -3904,7 +3904,6 @@ define i1 @cmpxchg_i8_monotonic_monotonic_val1(i8* %ptr, i8 signext %cmp, i8 sig
; RV64IA-NEXT: bnez a5, .LBB48_1
; RV64IA-NEXT: .LBB48_3:
; RV64IA-NEXT: and a0, a2, a4
; RV64IA-NEXT: sext.w a0, a0
; RV64IA-NEXT: xor a0, a1, a0
; RV64IA-NEXT: seqz a0, a0
; RV64IA-NEXT: ret
@ -4077,7 +4076,6 @@ define i1 @cmpxchg_i16_monotonic_monotonic_val1(i16* %ptr, i16 signext %cmp, i16
; RV64IA-NEXT: bnez a4, .LBB50_1
; RV64IA-NEXT: .LBB50_3:
; RV64IA-NEXT: and a0, a2, a5
; RV64IA-NEXT: sext.w a0, a0
; RV64IA-NEXT: xor a0, a1, a0
; RV64IA-NEXT: seqz a0, a0
; RV64IA-NEXT: ret