96 lines
2.7 KiB
LLVM
96 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 -verify-machineinstrs -mattr=+m | FileCheck %s -check-prefixes=RV32
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; RUN: llc < %s -mtriple=riscv64 -verify-machineinstrs -mattr=+m | FileCheck %s -check-prefixes=RV64
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; Test case:
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; - Addition should be cheaper than multiplication
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; The following LLVM IR simulates:
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; int8_t flag2[8193];
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; void test(int i) {
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; int tmp = i * 2;
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; if (i * 2 > 8192) return ;
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; for (int j = 0; ; ++j) {
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; int offset = j * i + tmp;
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; flag2[offset] = 0;
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; if (offset + i > 8192) break;
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; }
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; }
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; After LSR:
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; int8_t flag2[8193];
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; void test(int i) {
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; int j = i * 2;
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; if (j > 8193) return ;
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; do {
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; flag2[j] = 0;
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; j += i;
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; } while (j < 8193);
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; }
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@flags2 = internal global [8193 x i8] zeroinitializer, align 32 ; <[8193 x i8]*> [#uses=1]
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define void @test(i32 signext %i) nounwind {
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; RV32-LABEL: test:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: slli a1, a0, 1
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; RV32-NEXT: lui a3, 2
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; RV32-NEXT: blt a3, a1, .LBB0_3
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; RV32-NEXT: # %bb.1: # %bb.preheader
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; RV32-NEXT: lui a2, %hi(flags2)
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; RV32-NEXT: addi a2, a2, %lo(flags2)
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; RV32-NEXT: addi a3, a3, 1
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; RV32-NEXT: .LBB0_2: # %bb
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; RV32-NEXT: # =>This Inner Loop Header: Depth=1
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; RV32-NEXT: add a4, a2, a1
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; RV32-NEXT: add a1, a1, a0
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; RV32-NEXT: sb zero, 0(a4)
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; RV32-NEXT: blt a1, a3, .LBB0_2
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; RV32-NEXT: .LBB0_3: # %return
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: slliw a1, a0, 1
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; RV64-NEXT: lui a4, 2
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; RV64-NEXT: blt a4, a1, .LBB0_3
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; RV64-NEXT: # %bb.1: # %bb.preheader
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; RV64-NEXT: li a2, 0
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; RV64-NEXT: lui a3, %hi(flags2)
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; RV64-NEXT: addi a3, a3, %lo(flags2)
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; RV64-NEXT: addiw a4, a4, 1
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; RV64-NEXT: .LBB0_2: # %bb
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; RV64-NEXT: # =>This Inner Loop Header: Depth=1
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; RV64-NEXT: mulw a5, a2, a0
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; RV64-NEXT: addw a5, a5, a1
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; RV64-NEXT: slli a6, a5, 32
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; RV64-NEXT: srli a6, a6, 32
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; RV64-NEXT: add a6, a3, a6
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; RV64-NEXT: sb zero, 0(a6)
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; RV64-NEXT: addw a5, a5, a0
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; RV64-NEXT: addiw a2, a2, 1
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; RV64-NEXT: blt a5, a4, .LBB0_2
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; RV64-NEXT: .LBB0_3: # %return
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; RV64-NEXT: ret
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entry:
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%k_addr.012 = shl i32 %i, 1
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%tmp14 = icmp sgt i32 %k_addr.012, 8192
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%tmp. = shl i32 %i, 1
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br i1 %tmp14, label %return, label %bb
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bb:
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%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]
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%tmp.15 = mul i32 %indvar, %i
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%tmp.16 = add i32 %tmp.15, %tmp.
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%gep.upgrd.1 = zext i32 %tmp.16 to i64
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%tmp = getelementptr [8193 x i8], [8193 x i8]* @flags2, i32 0, i64 %gep.upgrd.1
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store i8 0, i8* %tmp
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%tmp.17 = add i32 %tmp.16, %i
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%tmp.upgrd.2 = icmp sgt i32 %tmp.17, 8192
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%indvar.next = add i32 %indvar, 1
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br i1 %tmp.upgrd.2, label %return, label %bb
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return:
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ret void
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}
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