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910 Commits

Author SHA1 Message Date
zhoujingya f9a20984b5 [VENTUS][fix] Comment out illegal fmv.w.x instruction and change vmv instructions' format 
https://github.com/THU-DSP-LAB/llvm-project/issues/30
 2023-10-09 14:04:55 +08:00
zhoujingya 0a45eabde0 Revert "[VENTUS][RISCV][feat] Legalized vector parameters" 
This reverts commit 7bd98c0ff8.
 2023-10-08 17:31:53 +08:00
zhoujingya 8bea355dbe Revert "[VENTUS][RISCV][feat] Legalized vector parameters" 
This reverts commit 12195ac947.
 2023-10-08 17:31:09 +08:00
qinfan 12195ac947 [VENTUS][RISCV][feat] Legalized vector parameters 2023-10-08 11:28:04 +08:00
qinfan 7bd98c0ff8 [VENTUS][RISCV][feat] Legalized vector parameters 
Summary: LegaLegalized vector parameters, but not been added FileCheck now.

Test Plan: Legalized vector parameters

Differential Revision: http://www.tpt.com/D740
 2023-10-08 11:28:04 +08:00
zhoujingya 0e5eef6abb [VENTUS][fix] fix add instruction 
Summary:
fix addi instruction, there will be a hardware error when immediate is
negative number.

Test Plan: fix add instruction

Reviewers: zhoujing

Subscribers: zhoujing

Differential Revision: http://www.tpt.com/D722

Signed-off-by: qinfan <qinfan.wang@terapines.com>
 2023-09-08 10:32:17 +08:00
zhoujingya b7b8fa50ba [VENTUS][fix] Fix load instruction selection pattern for vastart 
In standard riscv vararg support, the varstart frame index will be stored in stack,
but because if the design of ventus, some code generation  will be like this
        vlw.v   v0, -44(v8)
        vadd.vi v1, v0, 4
        vsw.v   v1, -44(v8)
        \vlw12.v v0, 0(v0)
the last vlw12 instruction is actually illeagl, it should be vlw
 2023-09-05 14:41:10 +08:00
zhoujing 700020da1e [VENTUS][fix] Fix vastart builtin codegen 2023-08-09 17:07:15 +08:00
zhoujing 50b23dc21a [VENTUS][fix] Deprecating vmv.s.x and use vmv.v.x instead 
As required, vmv.s.x instruction may will later be deprecated
 2023-08-01 13:25:24 +08:00
zhoujing bfed578a87 [VENTUS][RISCV][fix] Fix illegal vmv instruction in libclc library 
Other than atomic functions library, there are no illegal instructions

Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-06-27 15:53:51 +08:00
yanming 58ce5c83b8 [VENTUS][RISCV] Fix VBranch instruction info and select codegen patterns. 2023-06-27 11:12:37 +08:00
yanming 6189c2e9e7 [VENTUS][RISCV] Add SETRPC and JOIN instruction definition. 2023-06-26 15:40:37 +08:00
zhoujing 7b8402802a [VENTUS][RISCV][fix] Fix calling convention 2023-06-25 22:03:04 +08:00
zhoujing a6e8ff959a [VENTUS][RISCV][fix] Add missing flags for building libclc 
The flags information are lost by previous merge commit `Merge libclc-vector-support`
 2023-06-21 10:59:48 +08:00
zhoujing 615705a6c6 [VENTUS][RISCV][fix] Fix calling convention 2023-06-19 17:21:04 +08:00
zhoujing 513412bb33 [VENTUS][RISCV][fix] Fix building libclc errors 2023-06-16 17:42:22 +08:00
zhoujing 6636793f64 Merge libclc-vector-support 2023-06-16 09:41:08 +08:00
zhoujing e54daab265 [VENTUS][RISCV][fix] Fix function call calling convention 2023-06-15 13:36:12 +08:00
zhoujing 53a932e665 [VENTUS][RISCV][fix] Modify calling convention for non-kernel function arguments based on private memory address 
In our previous calling convention design, all non-kernel arguments are passed
by VGPRS or TP stack, but when the arguments point to private memory address
space, the wrong memory access instructions will be generated, because private
memory based address is scalar register
 2023-06-14 21:26:53 +08:00
zhoujing e5e7a0047a [VENTUS][RISCV][fix] Fix local memory access error in kernel function 2023-06-12 16:22:45 +08:00
zhoujing 940da111a3 [VENTUS][RISCV][fix] Fix divergent analysis bug for store node 2023-06-12 14:50:55 +08:00
zhoujing faf6a0bcd9 [VENTUS][RISCV][fix] Add initial Tp stack size calculation 
Cause there are two stacks in Ventus, we need to seperate TP stack and SP stack,
this commit just add very initial support for TP stack size calculation
 2023-06-11 12:18:39 +08:00
zhoujing 033505de1d [VENTUS][RISCV][fix] Modify calling convention 2023-06-05 17:11:25 +08:00
zhoujing 967cb725c8 [VENTUS][RISCV][feat] Set ventus kernel for OpenCL kernel functions 2023-06-05 13:10:35 +08:00
zhoujingya ad23baaa51 [VENTUS][RISCV][feat] Add more floating point instructions pattern 
Signed-off-by: zhoujing <jing.zhou@terapines.com>
 2023-05-25 14:48:30 +08:00
zhoujingya 9d9283fa7b [VENTUS][RISCV][fix] Fix ventus abi and calling convention 
Kernel functions use sp as GPRs spill stack slots
Non-kernel functions use tp as VGPRs spill stack slots
 2023-04-20 15:27:52 +08:00
zhoujingya f28e6c5e38 [VENTUS][RISCV][feat] Add vararg backend support in ventus 
We adjust the stack growing direction early months for OpenCL, in order to be
compatible with current architecture, we need to do some modification to
support vararg
 2023-04-18 10:03:53 +08:00
Aries 438f1c92c4 Fix some build warnings 2023-01-19 09:45:27 +08:00
zhoujing 7e701d4ba1 Add support for float point trunc instruction match 2023-01-09 18:06:39 +08:00
Aries 0b43b70327 Fix bug in addressing space mapping 2023-01-03 10:45:58 +08:00
zhoujing 1fab7b80f3 Legalize operation for SETCC 2022-12-29 17:13:49 +08:00
Aries 17adb707e6 Fix bug in kernel arg memory offset calculation 2022-12-29 11:53:29 +08:00
Aries 424ea45e4f Update Ventus GPGPU ABI: X4 as stack pointer, V0-V31 as arguments registers etc 2022-12-28 13:11:22 +08:00
Aries e8368c07e1 Fix kernel argument lowering alignment bug. 2022-12-27 17:00:46 +08:00
Aries 3a9c32a024 Add initial vector support(calling convention fix). 2022-12-27 16:35:12 +08:00
Aries da5006ca8d Add support to lowering BITCAST and Constant Pool for zfinx etc 2022-12-27 13:39:46 +08:00
Aries 9be2c54215 Add initial vGPR + sGPRF32 (zfinx) support 2022-12-27 12:00:30 +08:00
Aries 7d7ef235fd Support f32 return type in VGPR 2022-12-27 11:21:08 +08:00
Aries 2f946d86ad Fix basicblock insertion ordering for ISD::SELECT lowering. 2022-12-22 17:47:03 +08:00
Aries cb6f30fbd7 Add initial support to lower ISD::SELECT into branch instructions in divergent execution path. 2022-12-22 17:17:02 +08:00
Aries b9da010dd5 [NFC] Refactor messy switch...case 2022-12-22 14:50:13 +08:00
Aries beb878e97c Add OpenCL addressing space mapping to RISCVAS. 
Add kernel argument lowering.
Clean up a few unrelated RVV code.
 2022-12-20 17:08:08 +08:00
Aries dee3135130 Drafting divergent related code, not working yet. 2022-12-19 18:11:34 +08:00
Aries c6b68cbedb Support move between vGPR and sGPR. 
Fix a few bugs in calling convention related lowering functions.
 2022-12-19 14:21:26 +08:00
Aries 4e0cd22745 Add vALU conditional branch instructions 2022-12-19 13:09:00 +08:00
Aries 894931f522 More clean up and fix build error. 2022-12-19 10:10:28 +08:00
Aries 521e83631d Roughly cleaned RVV instruction selection. 2022-12-19 09:40:05 +08:00
Aries 35633e31e3 In the middle of removing RVV code. 2022-12-16 18:04:43 +08:00
Aries f1eff7fcfe Very very early step to remove RVV features from code base. 2022-12-16 17:33:54 +08:00
Kazu Hirata 3c09ed006a [llvm] Use std::nullopt instead of None in comments (NFC) 
This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
 2022-12-04 17:12:44 -08:00