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llvm-project/llvm/lib/Target/RISCV
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Philip Reames 06e2b44c46 [RISCV] Optimize scalable frame setup when VLEN is precisely known 
If we know the exact value of VLEN, the frame offset adjustment for scalable stack slots becomes a fixed constant. This avoids the need to read vlenb, and may allow the offset to be folded into the immediate field of an add/sub.

We could go further here, and fold the offset into a single larger frame adjustment - instead of having a separate scalable adjustment step - but that requires a bit more code reorganization. I may (or may not) return to that in a future patch.

Differential Revision: https://reviews.llvm.org/D137593
 		2022-11-18 15:30:39 -08:00
..
AsmParser [RISCV][CodeGen] add assertion to RISCVTargetStreamer getTargetStreamer() 2022-08-31 11:15:47 -07:00
Disassembler [RISCV] Implement assembler support for XVentanaCondOps 2022-11-14 09:01:54 -08:00
GISel [RISCV] Move GlobalISEL specific files to sub-directory [nfc] 2022-11-15 14:24:50 -08:00
MCA [RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV 2022-11-18 09:55:15 -08:00
MCTargetDesc [NFC][RISCV] Move getSEWLMULRatio function to header 2022-10-05 15:10:53 +01:00
TargetInfo [RISCV] Re-enable JIT support 2022-08-11 11:41:02 +02:00
CMakeLists.txt [RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV 2022-11-18 09:55:15 -08:00
RISCV.h [RISCV] Pre-RA expand pseudos pass 2022-07-31 23:19:00 +02:00
RISCV.td [RISCV] Move GlobalISEL specific files to sub-directory [nfc] 2022-11-15 14:24:50 -08:00
RISCVAsmPrinter.cpp [RISC-V][HWASAN] Fold variable into assert 2022-08-29 00:32:37 +02:00
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp [RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool. 2022-08-12 22:21:05 -07:00
RISCVExpandAtomicPseudoInsts.cpp [RISCV] Avoid redundant branch-to-branch when expanding cmpxchg 2022-08-17 13:49:15 +01:00
RISCVExpandPseudoInsts.cpp [RISCV] Add basic support for the sifive-7-series short forward branch optimization. 2022-10-17 13:56:22 -07:00
RISCVFrameLowering.cpp [RISCV] Optimize scalable frame setup when VLEN is precisely known 2022-11-18 15:30:39 -08:00
RISCVFrameLowering.h Revert "[RISCV] Enable the LocalStackSlotAllocation pass support" 2022-11-01 20:04:07 -07:00
RISCVGatherScatterLowering.cpp [RISCV] Extend strided load/store pattern matching to non-loop cases 2022-09-27 12:56:58 -07:00
RISCVISelDAGToDAG.cpp [RISCV] Add PACKH/PACKW/PACK to hasAllNBitUsers. 2022-11-13 23:57:52 -08:00
RISCVISelDAGToDAG.h [RISCV] Improve selection of PACK/PACKW for AssertZExt input. 2022-11-13 16:00:45 -08:00
RISCVISelLowering.cpp [RISCV] Make lowerVECTOR_SHUFFLEAsVSlidedown follow source until not EXTRACT_SUBVECTOR. 2022-11-17 22:32:53 -08:00
RISCVISelLowering.h [AMDGPU] Allow finer grain control of an unaligned access speed 2022-11-17 09:23:53 -08:00
RISCVInsertVSETVLI.cpp [RISCV] Map pseudos to their BaseInstr to reduce cases 2022-10-27 16:50:15 +08:00
RISCVInstrFormats.td [RISCV] Define custom-N opcodes 2022-11-04 10:05:30 -07:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td [RISCV] Use OPCFG format record for vsetvli in tablgen. NFC 2022-11-10 21:08:07 -08:00
RISCVInstrInfo.cpp [MachineCombiner][RISCV] Add fmadd/fmsub/fnmsub instructions patterns 2022-11-17 13:24:04 +03:00
RISCVInstrInfo.h [MachineCombiner][RISCV] Add fmadd/fmsub/fnmsub instructions patterns 2022-11-17 13:24:04 +03:00
RISCVInstrInfo.td [RISCV] Implement assembler support for XVentanaCondOps 2022-11-14 09:01:54 -08:00
RISCVInstrInfoA.td [RISCV] Add target feature to force-enable atomics 2022-08-09 16:04:46 +02:00
RISCVInstrInfoC.td [RISCV] : Add support for simm10_lsb0000nonzero operand. 2022-08-26 14:37:37 +08:00
RISCVInstrInfoD.td [RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven. 2022-10-26 14:36:49 -07:00
RISCVInstrInfoF.td [RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven. 2022-10-26 14:36:49 -07:00
RISCVInstrInfoM.td [RISCV][Clang] Add support for Zmmul extension 2022-07-18 20:26:08 -04:00
RISCVInstrInfoV.td [RISCV] Improve formatting of Sched lists in tablegen. NFC 2022-11-15 19:19:55 -08:00
RISCVInstrInfoVPseudos.td [RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV 2022-11-18 09:55:15 -08:00
RISCVInstrInfoVSDPatterns.td [RISCV] Use _TIED form of VFWADD(U)_WV/VFWSUB(U)_WV to avoid early clobber. 2022-10-03 21:44:08 -07:00
RISCVInstrInfoVVLPatterns.td [VP][RISCV] Add vp.nearbyint and RISC-V support. 2022-11-16 14:05:35 +08:00
RISCVInstrInfoXVentana.td [RISCV] Implement assembler support for XVentanaCondOps 2022-11-14 09:01:54 -08:00
RISCVInstrInfoZb.td [RISCV] Expand i32 abs to negw+max at isel. 2022-11-14 19:44:05 -08:00
RISCVInstrInfoZfh.td [RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven. 2022-10-26 14:36:49 -07:00
RISCVInstrInfoZicbo.td [RISCV][NFC] Fix typo in comment in RISCVInstrInfoZicbo.td 2022-09-01 13:49:55 +01:00
RISCVInstrInfoZk.td
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RISCVMCInstLower.cpp [RISCV] Pre-RA expand pseudos pass 2022-07-31 23:19:00 +02:00
RISCVMachineFunctionInfo.cpp [RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments. 2022-10-04 15:39:10 -07:00
RISCVMachineFunctionInfo.h [RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments. 2022-10-04 15:39:10 -07:00
RISCVMacroFusion.cpp [RISCV] Be more strict about LUI+ADDI macrofusion pre-RA. 2022-08-21 10:58:15 -07:00
RISCVMacroFusion.h [RISCV] Add macrofusion infrastructure and one example usage. 2022-06-23 08:38:39 -07:00
RISCVMakeCompressible.cpp [RISCV] Fix wrong register rename for store value during make-compressible optimization 2022-07-08 18:07:17 +08:00
RISCVMergeBaseOffset.cpp [RISCV] Fix operand number in debug message in RISCVMergeBaseOffset. 2022-08-02 15:27:23 -07:00
RISCVRedundantCopyElimination.cpp [RISCV] Use analyzeBranch in RISCVRedundantCopyElimination. 2022-08-29 09:05:53 -07:00
RISCVRegisterInfo.cpp [RISCV] Optimize scalable frame offset calculation when VLEN is precisely known 2022-11-18 09:56:55 -08:00
RISCVRegisterInfo.h PEI should be able to use backward walk in replaceFrameIndicesBackward. 2022-11-18 15:57:34 +01:00
RISCVRegisterInfo.td [RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI 2022-08-24 14:16:20 +00:00
RISCVSExtWRemoval.cpp [RISCV] Add PseudoCCMOVGPR to RISCVSExtWRemoval. 2022-11-14 13:39:00 -08:00
RISCVSchedRocket.td [RISCV] Merge WriteLDW and WriteLDWU schedule classes. 2022-10-28 11:57:33 -07:00
RISCVSchedSiFive7.td [RISCV] Merge WriteLDW and WriteLDWU schedule classes. 2022-10-28 11:57:33 -07:00
RISCVSchedule.td [RISCV] Merge WriteLDW and WriteLDWU schedule classes. 2022-10-28 11:57:33 -07:00
RISCVScheduleV.td [RISCV][CodeGen] Chapter of vector instruction type corresponds with chapters in RISCV vector specification. NFC 2022-11-18 10:30:08 -08:00
RISCVScheduleZb.td [RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC 2022-09-23 21:38:42 -07:00
RISCVSubtarget.cpp [RISCV] Move GlobalISEL specific files to sub-directory [nfc] 2022-11-15 14:24:50 -08:00
RISCVSubtarget.h [RISCV] Implement assembler support for XVentanaCondOps 2022-11-14 09:01:54 -08:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp [RISCV] Adjust RV64I data layout by using n32:64 in layout string 2022-10-28 08:27:03 -07:00
RISCVTargetMachine.h [llvm] Remove redundaunt virtual specifiers (NFC) 2022-07-24 21:50:35 -07:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp [VP][RISCV] Add vp.nearbyint and RISC-V support. 2022-11-16 14:05:35 +08:00
RISCVTargetTransformInfo.h [LV][RISCV] Disable vectorization of epilogue loops 2022-10-25 14:28:02 -07:00