forked from OSchip/llvm-project
366 lines
13 KiB
LLVM
366 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP
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declare half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a)
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declare float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a)
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declare double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)
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declare fp128 @llvm.vector.reduce.fmin.v1f128(<1 x fp128> %a)
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declare half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
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declare half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)
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declare float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
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declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
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declare float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
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define half @test_v1f16(<1 x half> %a) nounwind {
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; CHECK-LABEL: test_v1f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call nnan half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a)
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ret half %b
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}
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define float @test_v1f32(<1 x float> %a) nounwind {
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; CHECK-LABEL: test_v1f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
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; CHECK-NEXT: ret
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%b = call nnan float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a)
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ret float %b
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}
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define double @test_v1f64(<1 x double> %a) nounwind {
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; CHECK-LABEL: test_v1f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call nnan double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)
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ret double %b
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}
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define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v1f128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call nnan fp128 @llvm.vector.reduce.fmin.v1f128(<1 x fp128> %a)
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ret fp128 %b
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}
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define half @test_v4f16(<4 x half> %a) nounwind {
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; CHECK-NOFP-LABEL: test_v4f16:
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; CHECK-NOFP: // %bb.0:
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; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NOFP-NEXT: mov h1, v0.h[1]
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; CHECK-NOFP-NEXT: fcvt s2, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s1, s2, s1
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; CHECK-NOFP-NEXT: mov h2, v0.h[2]
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; CHECK-NOFP-NEXT: mov h0, v0.h[3]
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcvt s2, h2
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s1, s1, s2
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s0, s1, s0
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: ret
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;
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; CHECK-FP-LABEL: test_v4f16:
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; CHECK-FP: // %bb.0:
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; CHECK-FP-NEXT: fminnmv h0, v0.4h
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; CHECK-FP-NEXT: ret
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%b = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
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ret half %b
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}
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define half @test_v4f16_ninf(<4 x half> %a) nounwind {
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; CHECK-NOFP-LABEL: test_v4f16_ninf:
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; CHECK-NOFP: // %bb.0:
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; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NOFP-NEXT: mov h1, v0.h[1]
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; CHECK-NOFP-NEXT: fcvt s2, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s1, s2, s1
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; CHECK-NOFP-NEXT: mov h2, v0.h[2]
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; CHECK-NOFP-NEXT: mov h0, v0.h[3]
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcvt s2, h2
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s1, s1, s2
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s0, s1, s0
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: ret
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;
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; CHECK-FP-LABEL: test_v4f16_ninf:
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; CHECK-FP: // %bb.0:
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; CHECK-FP-NEXT: fminnmv h0, v0.4h
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; CHECK-FP-NEXT: ret
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%b = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
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ret half %b
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}
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define half @test_v11f16(<11 x half> %a) nounwind {
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; CHECK-NOFP-LABEL: test_v11f16:
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; CHECK-NOFP: // %bb.0:
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; CHECK-NOFP-NEXT: ldr h16, [sp, #8]
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: ldr h17, [sp]
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s2, h2
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; CHECK-NOFP-NEXT: adrp x8, .LCPI6_0
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; CHECK-NOFP-NEXT: fcvt s16, h16
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; CHECK-NOFP-NEXT: fcvt s3, h3
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; CHECK-NOFP-NEXT: fcvt s17, h17
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; CHECK-NOFP-NEXT: fcmp s1, s16
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; CHECK-NOFP-NEXT: fcsel s1, s1, s16, lt
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; CHECK-NOFP-NEXT: fcmp s0, s17
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; CHECK-NOFP-NEXT: ldr h16, [sp, #16]
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; CHECK-NOFP-NEXT: fcsel s0, s0, s17, lt
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcvt s16, h16
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fcmp s2, s16
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcsel s1, s2, s16, lt
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; CHECK-NOFP-NEXT: ldr h2, [x8, :lo12:.LCPI6_0]
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; CHECK-NOFP-NEXT: mov w8, #2139095040
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcvt s2, h2
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; CHECK-NOFP-NEXT: fmov s16, w8
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fcmp s3, s2
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
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; CHECK-NOFP-NEXT: fcvt s3, h4
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcmp s3, s2
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
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; CHECK-NOFP-NEXT: fcvt s3, h5
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcmp s3, s2
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
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; CHECK-NOFP-NEXT: fcvt s3, h6
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcmp s3, s2
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
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; CHECK-NOFP-NEXT: fcvt s3, h7
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcmp s3, s2
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: ret
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;
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; CHECK-FP-LABEL: test_v11f16:
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; CHECK-FP: // %bb.0:
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; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
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; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
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; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
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; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
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; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
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; CHECK-FP-NEXT: mov x8, sp
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; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
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; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
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; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
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; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
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; CHECK-FP-NEXT: movi v1.8h, #124, lsl #8
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; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
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; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8]
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; CHECK-FP-NEXT: add x8, sp, #8
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; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
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; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]
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; CHECK-FP-NEXT: add x8, sp, #16
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; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
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; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
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; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
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; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
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; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
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; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h
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; CHECK-FP-NEXT: fminnmv h0, v0.8h
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; CHECK-FP-NEXT: ret
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%b = call nnan half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)
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ret half %b
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}
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define half @test_v11f16_ninf(<11 x half> %a) nounwind {
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; CHECK-NOFP-LABEL: test_v11f16_ninf:
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; CHECK-NOFP: // %bb.0:
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; CHECK-NOFP-NEXT: ldr h16, [sp, #8]
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: ldr h17, [sp]
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s2, h2
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; CHECK-NOFP-NEXT: adrp x8, .LCPI7_0
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; CHECK-NOFP-NEXT: fcvt s16, h16
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; CHECK-NOFP-NEXT: fcvt s3, h3
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; CHECK-NOFP-NEXT: fcvt s17, h17
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; CHECK-NOFP-NEXT: fcmp s1, s16
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; CHECK-NOFP-NEXT: fcsel s1, s1, s16, lt
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; CHECK-NOFP-NEXT: fcmp s0, s17
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; CHECK-NOFP-NEXT: ldr h16, [sp, #16]
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; CHECK-NOFP-NEXT: fcsel s0, s0, s17, lt
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcvt s16, h16
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fcmp s2, s16
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcsel s1, s2, s16, lt
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; CHECK-NOFP-NEXT: ldr h2, [x8, :lo12:.LCPI7_0]
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; CHECK-NOFP-NEXT: mov w8, #57344
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; CHECK-NOFP-NEXT: movk w8, #18303, lsl #16
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcvt s2, h2
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; CHECK-NOFP-NEXT: fmov s16, w8
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fcmp s3, s2
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
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; CHECK-NOFP-NEXT: fcvt s3, h4
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcmp s3, s2
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
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; CHECK-NOFP-NEXT: fcvt s3, h5
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcmp s3, s2
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
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; CHECK-NOFP-NEXT: fcvt s3, h6
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcmp s3, s2
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
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; CHECK-NOFP-NEXT: fcvt s3, h7
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcmp s3, s2
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: fcvt h1, s1
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; CHECK-NOFP-NEXT: fcvt s0, h0
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; CHECK-NOFP-NEXT: fcvt s1, h1
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; CHECK-NOFP-NEXT: fminnm s0, s0, s1
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; CHECK-NOFP-NEXT: fcvt h0, s0
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; CHECK-NOFP-NEXT: ret
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;
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; CHECK-FP-LABEL: test_v11f16_ninf:
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; CHECK-FP: // %bb.0:
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; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
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; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
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; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
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; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
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; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
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; CHECK-FP-NEXT: mov x8, sp
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; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
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; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
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; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
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; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
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; CHECK-FP-NEXT: mvni v1.8h, #132, lsl #8
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; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8]
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; CHECK-FP-NEXT: add x8, sp, #8
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; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
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; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]
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; CHECK-FP-NEXT: add x8, sp, #16
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; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
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; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
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; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
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; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
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; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
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; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
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; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h
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; CHECK-FP-NEXT: fminnmv h0, v0.8h
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; CHECK-FP-NEXT: ret
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%b = call nnan ninf half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)
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ret half %b
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}
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define float @test_v3f32(<3 x float> %a) nounwind {
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; CHECK-LABEL: test_v3f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #2139095040
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: mov v0.s[3], v1.s[0]
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; CHECK-NEXT: fminnmv s0, v0.4s
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; CHECK-NEXT: ret
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%b = call nnan float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
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ret float %b
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}
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define float @test_v3f32_ninf(<3 x float> %a) nounwind {
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; CHECK-LABEL: test_v3f32_ninf:
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; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov w8, #2139095039
|
|
; CHECK-NEXT: fmov s1, w8
|
|
; CHECK-NEXT: mov v0.s[3], v1.s[0]
|
|
; CHECK-NEXT: fminnmv s0, v0.4s
|
|
; CHECK-NEXT: ret
|
|
%b = call nnan ninf float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
|
|
ret float %b
|
|
}
|
|
|
|
define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
|
|
; CHECK-LABEL: test_v2f128:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: b fminl
|
|
%b = call nnan fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
|
|
ret fp128 %b
|
|
}
|
|
|
|
define float @test_v16f32(<16 x float> %a) nounwind {
|
|
; CHECK-LABEL: test_v16f32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: fminnm v1.4s, v1.4s, v3.4s
|
|
; CHECK-NEXT: fminnm v0.4s, v0.4s, v2.4s
|
|
; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
|
|
; CHECK-NEXT: fminnmv s0, v0.4s
|
|
; CHECK-NEXT: ret
|
|
%b = call nnan float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
|
|
ret float %b
|
|
}
|