forked from OSchip/llvm-project
342 lines
7.6 KiB
LLVM
342 lines
7.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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; Test we can code generater patterns of the form:
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; fixed_length_vector = ISD::EXTRACT_SUBVECTOR scalable_vector, 0
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; scalable_vector = ISD::INSERT_SUBVECTOR scalable_vector, fixed_length_vector, 0
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;
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; NOTE: Currently shufflevector does not support scalable vectors so it cannot
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; be used to model the above operations. Instead these tests rely on knowing
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; how fixed length operation are lowered to scalable ones, with multiple blocks
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; ensuring insert/extract sequences are not folded away.
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-unknown-linux-gnu"
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; i8
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define void @subvector_v4i8(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v4i8:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr s0, [x0]
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: uunpklo z0.h, z0.b
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; CHECK-NEXT: st1b { z0.h }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <4 x i8>, ptr %in
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br label %bb1
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bb1:
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store <4 x i8> %a, ptr %out
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ret void
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}
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define void @subvector_v8i8(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v8i8:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: str d0, [x1]
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; CHECK-NEXT: ret
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%a = load <8 x i8>, ptr %in
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br label %bb1
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bb1:
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store <8 x i8> %a, ptr %out
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ret void
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}
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define void @subvector_v16i8(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v16i8:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%a = load <16 x i8>, ptr %in
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br label %bb1
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bb1:
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store <16 x i8> %a, ptr %out
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ret void
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}
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define void @subvector_v32i8(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v32i8:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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%a = load <32 x i8>, ptr %in
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br label %bb1
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bb1:
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store <32 x i8> %a, ptr %out
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ret void
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}
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; i16
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define void @subvector_v2i16(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v2i16:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: ldrh w8, [x0, #2]
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: str w8, [sp, #12]
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; CHECK-NEXT: ldrh w8, [x0]
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; CHECK-NEXT: str w8, [sp, #8]
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; CHECK-NEXT: ldr d0, [sp, #8]
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; CHECK-NEXT: st1h { z0.s }, p0, [x1]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%a = load <2 x i16>, ptr %in
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br label %bb1
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bb1:
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store <2 x i16> %a, ptr %out
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ret void
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}
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define void @subvector_v4i16(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v4i16:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: str d0, [x1]
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; CHECK-NEXT: ret
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%a = load <4 x i16>, ptr %in
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br label %bb1
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bb1:
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store <4 x i16> %a, ptr %out
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ret void
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}
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define void @subvector_v8i16(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v8i16:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%a = load <8 x i16>, ptr %in
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br label %bb1
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bb1:
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store <8 x i16> %a, ptr %out
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ret void
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}
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define void @subvector_v16i16(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v16i16:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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%a = load <16 x i16>, ptr %in
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br label %bb1
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bb1:
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store <16 x i16> %a, ptr %out
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ret void
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}
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; i32
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define void @subvector_v2i32(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v2i32:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: str d0, [x1]
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %in
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br label %bb1
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bb1:
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store <2 x i32> %a, ptr %out
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ret void
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}
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define void @subvector_v4i32(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v4i32:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%a = load <4 x i32>, ptr %in
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br label %bb1
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bb1:
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store <4 x i32> %a, ptr %out
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ret void
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}
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define void @subvector_v8i32(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v8i32:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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%a = load <8 x i32>, ptr %in
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br label %bb1
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bb1:
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store <8 x i32> %a, ptr %out
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ret void
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}
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; i64
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define void @subvector_v2i64(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v2i64:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%a = load <2 x i64>, ptr %in
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br label %bb1
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bb1:
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store <2 x i64> %a, ptr %out
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ret void
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}
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define void @subvector_v4i64(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v4i64:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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%a = load <4 x i64>, ptr %in
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br label %bb1
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bb1:
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store <4 x i64> %a, ptr %out
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ret void
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}
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; f16
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define void @subvector_v2f16(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v2f16:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: str w8, [x1]
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; CHECK-NEXT: ret
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%a = load <2 x half>, ptr %in
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br label %bb1
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bb1:
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store <2 x half> %a, ptr %out
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ret void
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}
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define void @subvector_v4f16(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v4f16:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: str d0, [x1]
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; CHECK-NEXT: ret
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%a = load <4 x half>, ptr %in
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br label %bb1
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bb1:
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store <4 x half> %a, ptr %out
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ret void
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}
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define void @subvector_v8f16(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v8f16:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%a = load <8 x half>, ptr %in
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br label %bb1
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bb1:
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store <8 x half> %a, ptr %out
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ret void
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}
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define void @subvector_v16f16(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v16f16:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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%a = load <16 x half>, ptr %in
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br label %bb1
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bb1:
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store <16 x half> %a, ptr %out
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ret void
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}
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; f32
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define void @subvector_v2f32(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v2f32:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: str d0, [x1]
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; CHECK-NEXT: ret
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%a = load <2 x float>, ptr %in
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br label %bb1
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bb1:
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store <2 x float> %a, ptr %out
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ret void
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}
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define void @subvector_v4f32(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v4f32:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%a = load <4 x float>, ptr %in
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br label %bb1
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bb1:
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store <4 x float> %a, ptr %out
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ret void
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}
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define void @subvector_v8f32(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v8f32:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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%a = load <8 x float>,ptr %in
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br label %bb1
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bb1:
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store <8 x float> %a, ptr %out
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ret void
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}
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; f64
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define void @subvector_v2f64(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v2f64:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%a = load <2 x double>, ptr %in
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br label %bb1
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bb1:
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store <2 x double> %a, ptr %out
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ret void
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}
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define void @subvector_v4f64(ptr %in, ptr %out) #0 {
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; CHECK-LABEL: subvector_v4f64:
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; CHECK: // %bb.0: // %bb1
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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%a = load <4 x double>, ptr %in
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br label %bb1
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bb1:
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store <4 x double> %a, ptr %out
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ret void
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}
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attributes #0 = { "target-features"="+sve" }
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