forked from OSchip/llvm-project
428 lines
15 KiB
LLVM
428 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: adrp x9, .LCPI0_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI0_0]
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; CHECK-NEXT: strh w8, [sp, #14]
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; CHECK-NEXT: strh w8, [sp, #12]
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; CHECK-NEXT: strh w8, [sp, #10]
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; CHECK-NEXT: strh w8, [sp, #8]
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; CHECK-NEXT: ldr d2, [sp, #8]
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <4 x i8> %op1, <4 x i8> %op2
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ret <4 x i8> %sel
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}
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define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: adrp x9, .LCPI1_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI1_0]
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; CHECK-NEXT: strb w8, [sp, #15]
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; CHECK-NEXT: strb w8, [sp, #14]
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; CHECK-NEXT: strb w8, [sp, #13]
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; CHECK-NEXT: strb w8, [sp, #12]
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; CHECK-NEXT: strb w8, [sp, #11]
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; CHECK-NEXT: strb w8, [sp, #10]
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; CHECK-NEXT: strb w8, [sp, #9]
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; CHECK-NEXT: strb w8, [sp, #8]
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; CHECK-NEXT: ldr d2, [sp, #8]
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <8 x i8> %op1, <8 x i8> %op2
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ret <8 x i8> %sel
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}
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define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: adrp x9, .LCPI2_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI2_0]
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; CHECK-NEXT: strb w8, [sp, #15]
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; CHECK-NEXT: strb w8, [sp, #14]
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; CHECK-NEXT: strb w8, [sp, #13]
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; CHECK-NEXT: strb w8, [sp, #12]
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; CHECK-NEXT: strb w8, [sp, #11]
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; CHECK-NEXT: strb w8, [sp, #10]
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; CHECK-NEXT: strb w8, [sp, #9]
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; CHECK-NEXT: strb w8, [sp, #8]
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; CHECK-NEXT: strb w8, [sp, #7]
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; CHECK-NEXT: strb w8, [sp, #6]
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; CHECK-NEXT: strb w8, [sp, #5]
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; CHECK-NEXT: strb w8, [sp, #4]
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; CHECK-NEXT: strb w8, [sp, #3]
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; CHECK-NEXT: strb w8, [sp, #2]
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; CHECK-NEXT: strb w8, [sp, #1]
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; CHECK-NEXT: strb w8, [sp]
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; CHECK-NEXT: ldr q2, [sp]
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <16 x i8> %op1, <16 x i8> %op2
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ret <16 x i8> %sel
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}
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define void @select_v32i8(ptr %a, ptr %b, i1 %mask) #0 {
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; CHECK-LABEL: select_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w2, #0x1
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; CHECK-NEXT: adrp x9, .LCPI3_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x0, #16]
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; CHECK-NEXT: ldr q2, [x1]
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; CHECK-NEXT: ldr q3, [x1, #16]
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; CHECK-NEXT: strb w8, [sp, #15]
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; CHECK-NEXT: strb w8, [sp, #14]
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; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI3_0]
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; CHECK-NEXT: strb w8, [sp, #13]
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; CHECK-NEXT: strb w8, [sp, #12]
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; CHECK-NEXT: strb w8, [sp, #11]
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; CHECK-NEXT: strb w8, [sp, #10]
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; CHECK-NEXT: strb w8, [sp, #9]
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; CHECK-NEXT: strb w8, [sp, #8]
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; CHECK-NEXT: strb w8, [sp, #7]
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; CHECK-NEXT: strb w8, [sp, #6]
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; CHECK-NEXT: strb w8, [sp, #5]
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; CHECK-NEXT: strb w8, [sp, #4]
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; CHECK-NEXT: strb w8, [sp, #3]
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; CHECK-NEXT: strb w8, [sp, #2]
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; CHECK-NEXT: strb w8, [sp, #1]
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; CHECK-NEXT: strb w8, [sp]
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; CHECK-NEXT: ldr q4, [sp]
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; CHECK-NEXT: eor z5.d, z4.d, z5.d
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; CHECK-NEXT: and z1.d, z1.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z4.d
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; CHECK-NEXT: and z2.d, z2.d, z5.d
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; CHECK-NEXT: and z3.d, z3.d, z5.d
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; CHECK-NEXT: orr z0.d, z0.d, z2.d
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; CHECK-NEXT: orr z1.d, z1.d, z3.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%op1 = load volatile <32 x i8>, ptr %a
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%op2 = load volatile <32 x i8>, ptr %b
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%sel = select i1 %mask, <32 x i8> %op1, <32 x i8> %op2
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store <32 x i8> %sel, ptr %a
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ret void
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}
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define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: adrp x9, .LCPI4_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI4_0]
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; CHECK-NEXT: stp w8, w8, [sp, #8]
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; CHECK-NEXT: ldr d2, [sp, #8]
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <2 x i16> %op1, <2 x i16> %op2
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ret <2 x i16> %sel
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}
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define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: adrp x9, .LCPI5_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI5_0]
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; CHECK-NEXT: strh w8, [sp, #14]
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; CHECK-NEXT: strh w8, [sp, #12]
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; CHECK-NEXT: strh w8, [sp, #10]
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; CHECK-NEXT: strh w8, [sp, #8]
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; CHECK-NEXT: ldr d2, [sp, #8]
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <4 x i16> %op1, <4 x i16> %op2
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ret <4 x i16> %sel
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}
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define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: adrp x9, .LCPI6_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI6_0]
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; CHECK-NEXT: strh w8, [sp, #14]
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; CHECK-NEXT: strh w8, [sp, #12]
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; CHECK-NEXT: strh w8, [sp, #10]
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; CHECK-NEXT: strh w8, [sp, #8]
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; CHECK-NEXT: strh w8, [sp, #6]
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; CHECK-NEXT: strh w8, [sp, #4]
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; CHECK-NEXT: strh w8, [sp, #2]
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; CHECK-NEXT: strh w8, [sp]
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; CHECK-NEXT: ldr q2, [sp]
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <8 x i16> %op1, <8 x i16> %op2
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ret <8 x i16> %sel
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}
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define void @select_v16i16(ptr %a, ptr %b, i1 %mask) #0 {
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; CHECK-LABEL: select_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w2, #0x1
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; CHECK-NEXT: adrp x9, .LCPI7_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x0, #16]
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; CHECK-NEXT: ldr q2, [x1]
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; CHECK-NEXT: ldr q3, [x1, #16]
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; CHECK-NEXT: strh w8, [sp, #14]
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; CHECK-NEXT: strh w8, [sp, #12]
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; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI7_0]
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; CHECK-NEXT: strh w8, [sp, #10]
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; CHECK-NEXT: strh w8, [sp, #8]
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; CHECK-NEXT: strh w8, [sp, #6]
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; CHECK-NEXT: strh w8, [sp, #4]
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; CHECK-NEXT: strh w8, [sp, #2]
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; CHECK-NEXT: strh w8, [sp]
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; CHECK-NEXT: ldr q4, [sp]
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; CHECK-NEXT: eor z5.d, z4.d, z5.d
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; CHECK-NEXT: and z1.d, z1.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z4.d
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; CHECK-NEXT: and z2.d, z2.d, z5.d
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; CHECK-NEXT: and z3.d, z3.d, z5.d
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; CHECK-NEXT: orr z0.d, z0.d, z2.d
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; CHECK-NEXT: orr z1.d, z1.d, z3.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%op1 = load volatile <16 x i16>, ptr %a
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%op2 = load volatile <16 x i16>, ptr %b
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%sel = select i1 %mask, <16 x i16> %op1, <16 x i16> %op2
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store <16 x i16> %sel, ptr %a
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ret void
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}
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define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: adrp x9, .LCPI8_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI8_0]
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; CHECK-NEXT: stp w8, w8, [sp, #8]
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; CHECK-NEXT: ldr d2, [sp, #8]
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <2 x i32> %op1, <2 x i32> %op2
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ret <2 x i32> %sel
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}
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define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: adrp x9, .LCPI9_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI9_0]
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; CHECK-NEXT: stp w8, w8, [sp, #8]
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; CHECK-NEXT: stp w8, w8, [sp]
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; CHECK-NEXT: ldr q2, [sp]
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <4 x i32> %op1, <4 x i32> %op2
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ret <4 x i32> %sel
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}
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define void @select_v8i32(ptr %a, ptr %b, i1 %mask) #0 {
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; CHECK-LABEL: select_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w2, #0x1
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; CHECK-NEXT: adrp x9, .LCPI10_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x0, #16]
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; CHECK-NEXT: ldr q2, [x1]
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; CHECK-NEXT: ldr q3, [x1, #16]
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; CHECK-NEXT: stp w8, w8, [sp, #8]
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; CHECK-NEXT: stp w8, w8, [sp]
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; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI10_0]
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; CHECK-NEXT: ldr q4, [sp]
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; CHECK-NEXT: eor z5.d, z4.d, z5.d
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; CHECK-NEXT: and z1.d, z1.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z4.d
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; CHECK-NEXT: and z2.d, z2.d, z5.d
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; CHECK-NEXT: and z3.d, z3.d, z5.d
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; CHECK-NEXT: orr z0.d, z0.d, z2.d
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; CHECK-NEXT: orr z1.d, z1.d, z3.d
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: add sp, sp, #16
|
|
; CHECK-NEXT: ret
|
|
%op1 = load volatile <8 x i32>, ptr %a
|
|
%op2 = load volatile <8 x i32>, ptr %b
|
|
%sel = select i1 %mask, <8 x i32> %op1, <8 x i32> %op2
|
|
store <8 x i32> %sel, ptr %a
|
|
ret void
|
|
}
|
|
|
|
define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) #0 {
|
|
; CHECK-LABEL: select_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: tst w0, #0x1
|
|
; CHECK-NEXT: mov x9, #-1
|
|
; CHECK-NEXT: csetm x8, ne
|
|
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fmov d3, x9
|
|
; CHECK-NEXT: fmov d2, x8
|
|
; CHECK-NEXT: eor z3.d, z2.d, z3.d
|
|
; CHECK-NEXT: and z0.d, z0.d, z2.d
|
|
; CHECK-NEXT: and z1.d, z1.d, z3.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z1.d
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%sel = select i1 %mask, <1 x i64> %op1, <1 x i64> %op2
|
|
ret <1 x i64> %sel
|
|
}
|
|
|
|
define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) #0 {
|
|
; CHECK-LABEL: select_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: tst w0, #0x1
|
|
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: adrp x9, .LCPI12_0
|
|
; CHECK-NEXT: csetm x8, ne
|
|
; CHECK-NEXT: stp x8, x8, [sp, #-16]!
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
|
; CHECK-NEXT: ldr q2, [sp]
|
|
; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI12_0]
|
|
; CHECK-NEXT: and z0.d, z0.d, z2.d
|
|
; CHECK-NEXT: eor z3.d, z2.d, z3.d
|
|
; CHECK-NEXT: and z1.d, z1.d, z3.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z1.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: add sp, sp, #16
|
|
; CHECK-NEXT: ret
|
|
%sel = select i1 %mask, <2 x i64> %op1, <2 x i64> %op2
|
|
ret <2 x i64> %sel
|
|
}
|
|
|
|
define void @select_v4i64(ptr %a, ptr %b, i1 %mask) #0 {
|
|
; CHECK-LABEL: select_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: tst w2, #0x1
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: csetm x8, ne
|
|
; CHECK-NEXT: ldr q1, [x0, #16]
|
|
; CHECK-NEXT: ldr q2, [x1]
|
|
; CHECK-NEXT: adrp x9, .LCPI13_0
|
|
; CHECK-NEXT: ldr q3, [x1, #16]
|
|
; CHECK-NEXT: stp x8, x8, [sp, #-16]!
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
|
; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI13_0]
|
|
; CHECK-NEXT: ldr q5, [sp]
|
|
; CHECK-NEXT: eor z4.d, z5.d, z4.d
|
|
; CHECK-NEXT: and z1.d, z1.d, z5.d
|
|
; CHECK-NEXT: and z0.d, z0.d, z5.d
|
|
; CHECK-NEXT: and z2.d, z2.d, z4.d
|
|
; CHECK-NEXT: and z3.d, z3.d, z4.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z2.d
|
|
; CHECK-NEXT: orr z1.d, z1.d, z3.d
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: add sp, sp, #16
|
|
; CHECK-NEXT: ret
|
|
%op1 = load volatile <4 x i64>, ptr %a
|
|
%op2 = load volatile <4 x i64>, ptr %b
|
|
%sel = select i1 %mask, <4 x i64> %op1, <4 x i64> %op2
|
|
store <4 x i64> %sel, ptr %a
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { "target-features"="+sve" }
|