forked from OSchip/llvm-project
636 lines
21 KiB
LLVM
636 lines
21 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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;
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; SDIV
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;
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define <4 x i8> @sdiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
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; CHECK-LABEL: sdiv_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: lsl z1.h, p0/m, z1.h, z2.h
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; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z2.h
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; CHECK-NEXT: asr z1.h, p0/m, z1.h, z2.h
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; CHECK-NEXT: asr z0.h, p0/m, z0.h, z2.h
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; CHECK-NEXT: sunpklo z1.s, z1.h
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; CHECK-NEXT: sunpklo z0.s, z0.h
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <4 x i8> %op1, %op2
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ret <4 x i8> %res
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}
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define <8 x i8> @sdiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
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; CHECK-LABEL: sdiv_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: sunpklo z1.h, z1.b
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; CHECK-NEXT: sunpklo z0.h, z0.b
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; CHECK-NEXT: sunpkhi z2.s, z1.h
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; CHECK-NEXT: sunpkhi z3.s, z0.h
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; CHECK-NEXT: sunpklo z1.s, z1.h
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; CHECK-NEXT: sunpklo z0.s, z0.h
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; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s
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; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
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; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <8 x i8> %op1, %op2
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ret <8 x i8> %res
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}
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define <16 x i8> @sdiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
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; CHECK-LABEL: sdiv_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: sunpkhi z2.h, z1.b
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; CHECK-NEXT: sunpkhi z3.h, z0.b
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: sunpklo z1.h, z1.b
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; CHECK-NEXT: sunpkhi z4.s, z2.h
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; CHECK-NEXT: sunpkhi z5.s, z3.h
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; CHECK-NEXT: sunpklo z2.s, z2.h
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; CHECK-NEXT: sunpklo z3.s, z3.h
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; CHECK-NEXT: sunpklo z0.h, z0.b
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; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s
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; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s
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; CHECK-NEXT: sunpkhi z3.s, z1.h
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; CHECK-NEXT: sunpkhi z5.s, z0.h
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; CHECK-NEXT: sunpklo z1.s, z1.h
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; CHECK-NEXT: sunpklo z0.s, z0.h
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; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z5.s
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; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: uzp1 z1.h, z2.h, z4.h
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; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h
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; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <16 x i8> %op1, %op2
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ret <16 x i8> %res
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}
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define void @sdiv_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
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; CHECK-LABEL: sdiv_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q3, q0, [x1]
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: ldp q2, q1, [x0]
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; CHECK-NEXT: sunpkhi z4.h, z0.b
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; CHECK-NEXT: sunpklo z0.h, z0.b
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; CHECK-NEXT: sunpkhi z6.s, z4.h
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; CHECK-NEXT: sunpklo z4.s, z4.h
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; CHECK-NEXT: sunpkhi z16.s, z0.h
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; CHECK-NEXT: sunpklo z0.s, z0.h
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; CHECK-NEXT: sunpkhi z5.h, z1.b
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; CHECK-NEXT: sunpklo z1.h, z1.b
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; CHECK-NEXT: sunpkhi z7.s, z5.h
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; CHECK-NEXT: sunpklo z5.s, z5.h
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; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s
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; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s
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; CHECK-NEXT: sunpkhi z5.s, z1.h
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; CHECK-NEXT: sunpklo z1.s, z1.h
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; CHECK-NEXT: uzp1 z4.h, z4.h, z6.h
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; CHECK-NEXT: sdivr z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: sunpkhi z1.h, z3.b
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; CHECK-NEXT: sunpkhi z6.h, z2.b
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; CHECK-NEXT: sdiv z5.s, p0/m, z5.s, z16.s
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; CHECK-NEXT: sunpkhi z7.s, z1.h
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; CHECK-NEXT: sunpkhi z16.s, z6.h
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; CHECK-NEXT: sunpklo z1.s, z1.h
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; CHECK-NEXT: sunpklo z6.s, z6.h
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; CHECK-NEXT: sunpklo z3.h, z3.b
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; CHECK-NEXT: sunpklo z2.h, z2.b
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; CHECK-NEXT: sdivr z7.s, p0/m, z7.s, z16.s
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; CHECK-NEXT: sdivr z1.s, p0/m, z1.s, z6.s
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; CHECK-NEXT: sunpkhi z6.s, z3.h
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; CHECK-NEXT: sunpkhi z16.s, z2.h
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; CHECK-NEXT: sunpklo z3.s, z3.h
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; CHECK-NEXT: sunpklo z2.s, z2.h
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; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z16.s
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; CHECK-NEXT: sdiv z2.s, p0/m, z2.s, z3.s
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; CHECK-NEXT: uzp1 z1.h, z1.h, z7.h
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; CHECK-NEXT: uzp1 z2.h, z2.h, z6.h
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; CHECK-NEXT: uzp1 z0.h, z0.h, z5.h
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; CHECK-NEXT: uzp1 z1.b, z2.b, z1.b
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; CHECK-NEXT: uzp1 z0.b, z0.b, z4.b
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; CHECK-NEXT: stp q1, q0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <32 x i8>, <32 x i8>* %a
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%op2 = load <32 x i8>, <32 x i8>* %b
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%res = sdiv <32 x i8> %op1, %op2
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store <32 x i8> %res, <32 x i8>* %a
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ret void
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}
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define <2 x i16> @sdiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
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; CHECK-LABEL: sdiv_v2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI4_0
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI4_0]
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; CHECK-NEXT: lsl z1.s, p0/m, z1.s, z2.s
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; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z2.s
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; CHECK-NEXT: asr z1.s, p0/m, z1.s, z2.s
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; CHECK-NEXT: asr z0.s, p0/m, z0.s, z2.s
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; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <2 x i16> %op1, %op2
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ret <2 x i16> %res
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}
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define <4 x i16> @sdiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
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; CHECK-LABEL: sdiv_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: sunpklo z1.s, z1.h
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; CHECK-NEXT: sunpklo z0.s, z0.h
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; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <4 x i16> %op1, %op2
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ret <4 x i16> %res
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}
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define <8 x i16> @sdiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
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; CHECK-LABEL: sdiv_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: sunpkhi z2.s, z1.h
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; CHECK-NEXT: sunpkhi z3.s, z0.h
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; CHECK-NEXT: sunpklo z1.s, z1.h
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; CHECK-NEXT: sunpklo z0.s, z0.h
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; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s
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; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <8 x i16> %op1, %op2
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ret <8 x i16> %res
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}
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define void @sdiv_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
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; CHECK-LABEL: sdiv_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x1]
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: sunpkhi z6.s, z0.h
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; CHECK-NEXT: sunpklo z0.s, z0.h
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; CHECK-NEXT: ldp q3, q2, [x0]
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; CHECK-NEXT: sunpkhi z4.s, z1.h
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; CHECK-NEXT: sunpklo z1.s, z1.h
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; CHECK-NEXT: sunpkhi z5.s, z2.h
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; CHECK-NEXT: sunpklo z2.s, z2.h
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; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s
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; CHECK-NEXT: sunpkhi z5.s, z3.h
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; CHECK-NEXT: sunpklo z3.s, z3.h
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; CHECK-NEXT: sdiv z5.s, p0/m, z5.s, z6.s
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; CHECK-NEXT: sdivr z0.s, p0/m, z0.s, z3.s
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; CHECK-NEXT: sdivr z1.s, p0/m, z1.s, z2.s
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; CHECK-NEXT: uzp1 z0.h, z0.h, z5.h
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; CHECK-NEXT: uzp1 z1.h, z1.h, z4.h
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x i16>, <16 x i16>* %a
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%op2 = load <16 x i16>, <16 x i16>* %b
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%res = sdiv <16 x i16> %op1, %op2
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store <16 x i16> %res, <16 x i16>* %a
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ret void
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}
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define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
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; CHECK-LABEL: sdiv_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <2 x i32> %op1, %op2
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ret <2 x i32> %res
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}
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define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
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; CHECK-LABEL: sdiv_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <4 x i32> %op1, %op2
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ret <4 x i32> %res
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}
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define void @sdiv_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
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; CHECK-LABEL: sdiv_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: ldp q2, q3, [x1]
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; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z2.s
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; CHECK-NEXT: sdiv z1.s, p0/m, z1.s, z3.s
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <8 x i32>, <8 x i32>* %a
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%op2 = load <8 x i32>, <8 x i32>* %b
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%res = sdiv <8 x i32> %op1, %op2
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store <8 x i32> %res, <8 x i32>* %a
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ret void
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}
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define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
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; CHECK-LABEL: sdiv_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.d, vl1
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <1 x i64> %op1, %op2
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ret <1 x i64> %res
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}
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define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
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; CHECK-LABEL: sdiv_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <2 x i64> %op1, %op2
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ret <2 x i64> %res
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}
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define void @sdiv_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
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; CHECK-LABEL: sdiv_v4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: ldp q2, q3, [x1]
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; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z2.d
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; CHECK-NEXT: sdiv z1.d, p0/m, z1.d, z3.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <4 x i64>, <4 x i64>* %a
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%op2 = load <4 x i64>, <4 x i64>* %b
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%res = sdiv <4 x i64> %op1, %op2
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store <4 x i64> %res, <4 x i64>* %a
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ret void
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}
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;
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; UDIV
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;
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define <4 x i8> @udiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
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; CHECK-LABEL: udiv_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI14_0
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI14_0]
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; CHECK-NEXT: and z1.d, z1.d, z2.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: uunpklo z1.s, z1.h
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; CHECK-NEXT: uunpklo z0.s, z0.h
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; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = udiv <4 x i8> %op1, %op2
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ret <4 x i8> %res
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}
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define <8 x i8> @udiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
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; CHECK-LABEL: udiv_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: uunpklo z1.h, z1.b
|
|
; CHECK-NEXT: uunpklo z0.h, z0.b
|
|
; CHECK-NEXT: uunpkhi z2.s, z1.h
|
|
; CHECK-NEXT: uunpkhi z3.s, z0.h
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s
|
|
; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
|
|
; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = udiv <8 x i8> %op1, %op2
|
|
ret <8 x i8> %res
|
|
}
|
|
|
|
define <16 x i8> @udiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
|
|
; CHECK-LABEL: udiv_v16i8:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: uunpkhi z2.h, z1.b
|
|
; CHECK-NEXT: uunpkhi z3.h, z0.b
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: uunpklo z1.h, z1.b
|
|
; CHECK-NEXT: uunpkhi z4.s, z2.h
|
|
; CHECK-NEXT: uunpkhi z5.s, z3.h
|
|
; CHECK-NEXT: uunpklo z2.s, z2.h
|
|
; CHECK-NEXT: uunpklo z3.s, z3.h
|
|
; CHECK-NEXT: uunpklo z0.h, z0.b
|
|
; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s
|
|
; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s
|
|
; CHECK-NEXT: uunpkhi z3.s, z1.h
|
|
; CHECK-NEXT: uunpkhi z5.s, z0.h
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z5.s
|
|
; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s
|
|
; CHECK-NEXT: uzp1 z1.h, z2.h, z4.h
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h
|
|
; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = udiv <16 x i8> %op1, %op2
|
|
ret <16 x i8> %res
|
|
}
|
|
|
|
define void @udiv_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
|
|
; CHECK-LABEL: udiv_v32i8:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q3, q0, [x1]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: ldp q2, q1, [x0]
|
|
; CHECK-NEXT: uunpkhi z4.h, z0.b
|
|
; CHECK-NEXT: uunpklo z0.h, z0.b
|
|
; CHECK-NEXT: uunpkhi z6.s, z4.h
|
|
; CHECK-NEXT: uunpklo z4.s, z4.h
|
|
; CHECK-NEXT: uunpkhi z16.s, z0.h
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: uunpkhi z5.h, z1.b
|
|
; CHECK-NEXT: uunpklo z1.h, z1.b
|
|
; CHECK-NEXT: uunpkhi z7.s, z5.h
|
|
; CHECK-NEXT: uunpklo z5.s, z5.h
|
|
; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s
|
|
; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s
|
|
; CHECK-NEXT: uunpkhi z5.s, z1.h
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: uzp1 z4.h, z4.h, z6.h
|
|
; CHECK-NEXT: udivr z0.s, p0/m, z0.s, z1.s
|
|
; CHECK-NEXT: uunpkhi z1.h, z3.b
|
|
; CHECK-NEXT: uunpkhi z6.h, z2.b
|
|
; CHECK-NEXT: udiv z5.s, p0/m, z5.s, z16.s
|
|
; CHECK-NEXT: uunpkhi z7.s, z1.h
|
|
; CHECK-NEXT: uunpkhi z16.s, z6.h
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: uunpklo z6.s, z6.h
|
|
; CHECK-NEXT: uunpklo z3.h, z3.b
|
|
; CHECK-NEXT: uunpklo z2.h, z2.b
|
|
; CHECK-NEXT: udivr z7.s, p0/m, z7.s, z16.s
|
|
; CHECK-NEXT: udivr z1.s, p0/m, z1.s, z6.s
|
|
; CHECK-NEXT: uunpkhi z6.s, z3.h
|
|
; CHECK-NEXT: uunpkhi z16.s, z2.h
|
|
; CHECK-NEXT: uunpklo z3.s, z3.h
|
|
; CHECK-NEXT: uunpklo z2.s, z2.h
|
|
; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z16.s
|
|
; CHECK-NEXT: udiv z2.s, p0/m, z2.s, z3.s
|
|
; CHECK-NEXT: uzp1 z1.h, z1.h, z7.h
|
|
; CHECK-NEXT: uzp1 z2.h, z2.h, z6.h
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z5.h
|
|
; CHECK-NEXT: uzp1 z1.b, z2.b, z1.b
|
|
; CHECK-NEXT: uzp1 z0.b, z0.b, z4.b
|
|
; CHECK-NEXT: stp q1, q0, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <32 x i8>, <32 x i8>* %a
|
|
%op2 = load <32 x i8>, <32 x i8>* %b
|
|
%res = udiv <32 x i8> %op1, %op2
|
|
store <32 x i8> %res, <32 x i8>* %a
|
|
ret void
|
|
}
|
|
|
|
define <2 x i16> @udiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
|
|
; CHECK-LABEL: udiv_v2i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: adrp x8, .LCPI18_0
|
|
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI18_0]
|
|
; CHECK-NEXT: and z1.d, z1.d, z2.d
|
|
; CHECK-NEXT: and z0.d, z0.d, z2.d
|
|
; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = udiv <2 x i16> %op1, %op2
|
|
ret <2 x i16> %res
|
|
}
|
|
|
|
define <4 x i16> @udiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
|
|
; CHECK-LABEL: udiv_v4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = udiv <4 x i16> %op1, %op2
|
|
ret <4 x i16> %res
|
|
}
|
|
|
|
define <8 x i16> @udiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
|
|
; CHECK-LABEL: udiv_v8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: uunpkhi z2.s, z1.h
|
|
; CHECK-NEXT: uunpkhi z3.s, z0.h
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s
|
|
; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = udiv <8 x i16> %op1, %op2
|
|
ret <8 x i16> %res
|
|
}
|
|
|
|
define void @udiv_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
|
|
; CHECK-LABEL: udiv_v16i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x1]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: uunpkhi z6.s, z0.h
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: ldp q3, q2, [x0]
|
|
; CHECK-NEXT: uunpkhi z4.s, z1.h
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: uunpkhi z5.s, z2.h
|
|
; CHECK-NEXT: uunpklo z2.s, z2.h
|
|
; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s
|
|
; CHECK-NEXT: uunpkhi z5.s, z3.h
|
|
; CHECK-NEXT: uunpklo z3.s, z3.h
|
|
; CHECK-NEXT: udiv z5.s, p0/m, z5.s, z6.s
|
|
; CHECK-NEXT: udivr z0.s, p0/m, z0.s, z3.s
|
|
; CHECK-NEXT: udivr z1.s, p0/m, z1.s, z2.s
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z5.h
|
|
; CHECK-NEXT: uzp1 z1.h, z1.h, z4.h
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x i16>, <16 x i16>* %a
|
|
%op2 = load <16 x i16>, <16 x i16>* %b
|
|
%res = udiv <16 x i16> %op1, %op2
|
|
store <16 x i16> %res, <16 x i16>* %a
|
|
ret void
|
|
}
|
|
|
|
define <2 x i32> @udiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
|
|
; CHECK-LABEL: udiv_v2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
|
; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = udiv <2 x i32> %op1, %op2
|
|
ret <2 x i32> %res
|
|
}
|
|
|
|
define <4 x i32> @udiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
|
|
; CHECK-LABEL: udiv_v4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
|
; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = udiv <4 x i32> %op1, %op2
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
define void @udiv_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
|
|
; CHECK-LABEL: udiv_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: ldp q2, q3, [x1]
|
|
; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z2.s
|
|
; CHECK-NEXT: udiv z1.s, p0/m, z1.s, z3.s
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x i32>, <8 x i32>* %a
|
|
%op2 = load <8 x i32>, <8 x i32>* %b
|
|
%res = udiv <8 x i32> %op1, %op2
|
|
store <8 x i32> %res, <8 x i32>* %a
|
|
ret void
|
|
}
|
|
|
|
define <1 x i64> @udiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
|
|
; CHECK-LABEL: udiv_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl1
|
|
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
|
; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = udiv <1 x i64> %op1, %op2
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
define <2 x i64> @udiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
|
|
; CHECK-LABEL: udiv_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
|
; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = udiv <2 x i64> %op1, %op2
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @udiv_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
|
|
; CHECK-LABEL: udiv_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: ldp q2, q3, [x1]
|
|
; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z2.d
|
|
; CHECK-NEXT: udiv z1.d, p0/m, z1.d, z3.d
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <4 x i64>, <4 x i64>* %a
|
|
%op2 = load <4 x i64>, <4 x i64>* %b
|
|
%res = udiv <4 x i64> %op1, %op2
|
|
store <4 x i64> %res, <4 x i64>* %a
|
|
ret void
|
|
}
|
|
|
|
define void @udiv_constantsplat_v8i32(<8 x i32>* %a) #0 {
|
|
; CHECK-LABEL: udiv_constantsplat_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: adrp x8, .LCPI28_0
|
|
; CHECK-NEXT: adrp x9, .LCPI28_1
|
|
; CHECK-NEXT: ldp q1, q2, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI28_0]
|
|
; CHECK-NEXT: adrp x8, .LCPI28_2
|
|
; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI28_1]
|
|
; CHECK-NEXT: movprfx z5, z1
|
|
; CHECK-NEXT: umulh z5.s, p0/m, z5.s, z0.s
|
|
; CHECK-NEXT: sub z1.s, z1.s, z5.s
|
|
; CHECK-NEXT: umulh z0.s, p0/m, z0.s, z2.s
|
|
; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI28_2]
|
|
; CHECK-NEXT: sub z2.s, z2.s, z0.s
|
|
; CHECK-NEXT: lsr z1.s, p0/m, z1.s, z3.s
|
|
; CHECK-NEXT: lsr z2.s, p0/m, z2.s, z3.s
|
|
; CHECK-NEXT: add z1.s, z1.s, z5.s
|
|
; CHECK-NEXT: add z0.s, z2.s, z0.s
|
|
; CHECK-NEXT: lsr z1.s, p0/m, z1.s, z4.s
|
|
; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z4.s
|
|
; CHECK-NEXT: stp q1, q0, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x i32>, <8 x i32>* %a
|
|
%res = udiv <8 x i32> %op1, <i32 95, i32 95, i32 95, i32 95, i32 95, i32 95, i32 95, i32 95>
|
|
store <8 x i32> %res, <8 x i32>* %a
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { "target-features"="+sve" }
|