forked from OSchip/llvm-project
792 lines
24 KiB
LLVM
792 lines
24 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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;
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; ADD
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;
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define <4 x i8> @add_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
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; CHECK-LABEL: add_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: add z0.h, z0.h, z1.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = add <4 x i8> %op1, %op2
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ret <4 x i8> %res
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}
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define <8 x i8> @add_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
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; CHECK-LABEL: add_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: add z0.b, z0.b, z1.b
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = add <8 x i8> %op1, %op2
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ret <8 x i8> %res
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}
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define <16 x i8> @add_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
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; CHECK-LABEL: add_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: add z0.b, z0.b, z1.b
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = add <16 x i8> %op1, %op2
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ret <16 x i8> %res
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}
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define void @add_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
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; CHECK-LABEL: add_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ldp q2, q3, [x1]
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; CHECK-NEXT: add z0.b, z0.b, z2.b
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; CHECK-NEXT: add z1.b, z1.b, z3.b
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <32 x i8>, <32 x i8>* %a
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%op2 = load <32 x i8>, <32 x i8>* %b
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%res = add <32 x i8> %op1, %op2
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store <32 x i8> %res, <32 x i8>* %a
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ret void
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}
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define <2 x i16> @add_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
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; CHECK-LABEL: add_v2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: add z0.s, z0.s, z1.s
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = add <2 x i16> %op1, %op2
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ret <2 x i16> %res
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}
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define <4 x i16> @add_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
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; CHECK-LABEL: add_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: add z0.h, z0.h, z1.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = add <4 x i16> %op1, %op2
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ret <4 x i16> %res
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}
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define <8 x i16> @add_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
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; CHECK-LABEL: add_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: add z0.h, z0.h, z1.h
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = add <8 x i16> %op1, %op2
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ret <8 x i16> %res
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}
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define void @add_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
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; CHECK-LABEL: add_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ldp q2, q3, [x1]
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; CHECK-NEXT: add z0.h, z0.h, z2.h
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; CHECK-NEXT: add z1.h, z1.h, z3.h
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x i16>, <16 x i16>* %a
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%op2 = load <16 x i16>, <16 x i16>* %b
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%res = add <16 x i16> %op1, %op2
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store <16 x i16> %res, <16 x i16>* %a
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ret void
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}
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define <2 x i32> @add_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
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; CHECK-LABEL: add_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: add z0.s, z0.s, z1.s
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = add <2 x i32> %op1, %op2
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ret <2 x i32> %res
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}
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define <4 x i32> @add_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
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; CHECK-LABEL: add_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: add z0.s, z0.s, z1.s
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = add <4 x i32> %op1, %op2
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ret <4 x i32> %res
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}
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define void @add_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
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; CHECK-LABEL: add_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ldp q2, q3, [x1]
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; CHECK-NEXT: add z0.s, z0.s, z2.s
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; CHECK-NEXT: add z1.s, z1.s, z3.s
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <8 x i32>, <8 x i32>* %a
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%op2 = load <8 x i32>, <8 x i32>* %b
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%res = add <8 x i32> %op1, %op2
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store <8 x i32> %res, <8 x i32>* %a
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ret void
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}
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define <1 x i64> @add_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
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; CHECK-LABEL: add_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: add z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = add <1 x i64> %op1, %op2
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ret <1 x i64> %res
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}
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define <2 x i64> @add_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
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; CHECK-LABEL: add_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: add z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = add <2 x i64> %op1, %op2
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ret <2 x i64> %res
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}
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define void @add_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
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; CHECK-LABEL: add_v4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ldp q2, q3, [x1]
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; CHECK-NEXT: add z0.d, z0.d, z2.d
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; CHECK-NEXT: add z1.d, z1.d, z3.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <4 x i64>, <4 x i64>* %a
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%op2 = load <4 x i64>, <4 x i64>* %b
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%res = add <4 x i64> %op1, %op2
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store <4 x i64> %res, <4 x i64>* %a
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ret void
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}
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;
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; MUL
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;
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define <4 x i8> @mul_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
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; CHECK-LABEL: mul_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = mul <4 x i8> %op1, %op2
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ret <4 x i8> %res
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}
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define <8 x i8> @mul_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
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; CHECK-LABEL: mul_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.b, vl8
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = mul <8 x i8> %op1, %op2
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ret <8 x i8> %res
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}
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define <16 x i8> @mul_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
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; CHECK-LABEL: mul_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = mul <16 x i8> %op1, %op2
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ret <16 x i8> %res
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}
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define void @mul_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
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; CHECK-LABEL: mul_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: ldp q2, q3, [x1]
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; CHECK-NEXT: mul z0.b, p0/m, z0.b, z2.b
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; CHECK-NEXT: mul z1.b, p0/m, z1.b, z3.b
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <32 x i8>, <32 x i8>* %a
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%op2 = load <32 x i8>, <32 x i8>* %b
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%res = mul <32 x i8> %op1, %op2
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store <32 x i8> %res, <32 x i8>* %a
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ret void
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}
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define <2 x i16> @mul_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
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; CHECK-LABEL: mul_v2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = mul <2 x i16> %op1, %op2
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ret <2 x i16> %res
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}
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define <4 x i16> @mul_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
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; CHECK-LABEL: mul_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = mul <4 x i16> %op1, %op2
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ret <4 x i16> %res
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}
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define <8 x i16> @mul_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
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; CHECK-LABEL: mul_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = mul <8 x i16> %op1, %op2
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ret <8 x i16> %res
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}
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define void @mul_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
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; CHECK-LABEL: mul_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: ldp q2, q3, [x1]
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; CHECK-NEXT: mul z0.h, p0/m, z0.h, z2.h
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; CHECK-NEXT: mul z1.h, p0/m, z1.h, z3.h
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x i16>, <16 x i16>* %a
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%op2 = load <16 x i16>, <16 x i16>* %b
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%res = mul <16 x i16> %op1, %op2
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store <16 x i16> %res, <16 x i16>* %a
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ret void
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}
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define <2 x i32> @mul_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
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; CHECK-LABEL: mul_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = mul <2 x i32> %op1, %op2
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ret <2 x i32> %res
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}
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define <4 x i32> @mul_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
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; CHECK-LABEL: mul_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = mul <4 x i32> %op1, %op2
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ret <4 x i32> %res
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}
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define void @mul_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
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; CHECK-LABEL: mul_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: ldp q2, q3, [x1]
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; CHECK-NEXT: mul z0.s, p0/m, z0.s, z2.s
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; CHECK-NEXT: mul z1.s, p0/m, z1.s, z3.s
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <8 x i32>, <8 x i32>* %a
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%op2 = load <8 x i32>, <8 x i32>* %b
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%res = mul <8 x i32> %op1, %op2
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store <8 x i32> %res, <8 x i32>* %a
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ret void
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}
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define <1 x i64> @mul_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
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; CHECK-LABEL: mul_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.d, vl1
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = mul <1 x i64> %op1, %op2
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ret <1 x i64> %res
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}
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define <2 x i64> @mul_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
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; CHECK-LABEL: mul_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
|
; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = mul <2 x i64> %op1, %op2
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @mul_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
|
|
; CHECK-LABEL: mul_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: ldp q2, q3, [x1]
|
|
; CHECK-NEXT: mul z0.d, p0/m, z0.d, z2.d
|
|
; CHECK-NEXT: mul z1.d, p0/m, z1.d, z3.d
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <4 x i64>, <4 x i64>* %a
|
|
%op2 = load <4 x i64>, <4 x i64>* %b
|
|
%res = mul <4 x i64> %op1, %op2
|
|
store <4 x i64> %res, <4 x i64>* %a
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; SUB
|
|
;
|
|
|
|
define <4 x i8> @sub_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
|
|
; CHECK-LABEL: sub_v4i8:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
|
; CHECK-NEXT: sub z0.h, z0.h, z1.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = sub <4 x i8> %op1, %op2
|
|
ret <4 x i8> %res
|
|
}
|
|
|
|
define <8 x i8> @sub_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
|
|
; CHECK-LABEL: sub_v8i8:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
|
; CHECK-NEXT: sub z0.b, z0.b, z1.b
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = sub <8 x i8> %op1, %op2
|
|
ret <8 x i8> %res
|
|
}
|
|
|
|
define <16 x i8> @sub_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
|
|
; CHECK-LABEL: sub_v16i8:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
|
; CHECK-NEXT: sub z0.b, z0.b, z1.b
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = sub <16 x i8> %op1, %op2
|
|
ret <16 x i8> %res
|
|
}
|
|
|
|
define void @sub_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
|
|
; CHECK-LABEL: sub_v32i8:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ldp q2, q3, [x1]
|
|
; CHECK-NEXT: sub z0.b, z0.b, z2.b
|
|
; CHECK-NEXT: sub z1.b, z1.b, z3.b
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <32 x i8>, <32 x i8>* %a
|
|
%op2 = load <32 x i8>, <32 x i8>* %b
|
|
%res = sub <32 x i8> %op1, %op2
|
|
store <32 x i8> %res, <32 x i8>* %a
|
|
ret void
|
|
}
|
|
|
|
define <2 x i16> @sub_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
|
|
; CHECK-LABEL: sub_v2i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
|
; CHECK-NEXT: sub z0.s, z0.s, z1.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = sub <2 x i16> %op1, %op2
|
|
ret <2 x i16> %res
|
|
}
|
|
|
|
define <4 x i16> @sub_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
|
|
; CHECK-LABEL: sub_v4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
|
; CHECK-NEXT: sub z0.h, z0.h, z1.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = sub <4 x i16> %op1, %op2
|
|
ret <4 x i16> %res
|
|
}
|
|
|
|
define <8 x i16> @sub_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
|
|
; CHECK-LABEL: sub_v8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
|
; CHECK-NEXT: sub z0.h, z0.h, z1.h
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = sub <8 x i16> %op1, %op2
|
|
ret <8 x i16> %res
|
|
}
|
|
|
|
define void @sub_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
|
|
; CHECK-LABEL: sub_v16i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ldp q2, q3, [x1]
|
|
; CHECK-NEXT: sub z0.h, z0.h, z2.h
|
|
; CHECK-NEXT: sub z1.h, z1.h, z3.h
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x i16>, <16 x i16>* %a
|
|
%op2 = load <16 x i16>, <16 x i16>* %b
|
|
%res = sub <16 x i16> %op1, %op2
|
|
store <16 x i16> %res, <16 x i16>* %a
|
|
ret void
|
|
}
|
|
|
|
define <2 x i32> @sub_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
|
|
; CHECK-LABEL: sub_v2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
|
; CHECK-NEXT: sub z0.s, z0.s, z1.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = sub <2 x i32> %op1, %op2
|
|
ret <2 x i32> %res
|
|
}
|
|
|
|
define <4 x i32> @sub_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
|
|
; CHECK-LABEL: sub_v4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
|
; CHECK-NEXT: sub z0.s, z0.s, z1.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = sub <4 x i32> %op1, %op2
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
define void @sub_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
|
|
; CHECK-LABEL: sub_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ldp q2, q3, [x1]
|
|
; CHECK-NEXT: sub z0.s, z0.s, z2.s
|
|
; CHECK-NEXT: sub z1.s, z1.s, z3.s
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x i32>, <8 x i32>* %a
|
|
%op2 = load <8 x i32>, <8 x i32>* %b
|
|
%res = sub <8 x i32> %op1, %op2
|
|
store <8 x i32> %res, <8 x i32>* %a
|
|
ret void
|
|
}
|
|
|
|
define <1 x i64> @sub_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
|
|
; CHECK-LABEL: sub_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
|
; CHECK-NEXT: sub z0.d, z0.d, z1.d
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = sub <1 x i64> %op1, %op2
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
define <2 x i64> @sub_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
|
|
; CHECK-LABEL: sub_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
|
; CHECK-NEXT: sub z0.d, z0.d, z1.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = sub <2 x i64> %op1, %op2
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @sub_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
|
|
; CHECK-LABEL: sub_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ldp q2, q3, [x1]
|
|
; CHECK-NEXT: sub z0.d, z0.d, z2.d
|
|
; CHECK-NEXT: sub z1.d, z1.d, z3.d
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <4 x i64>, <4 x i64>* %a
|
|
%op2 = load <4 x i64>, <4 x i64>* %b
|
|
%res = sub <4 x i64> %op1, %op2
|
|
store <4 x i64> %res, <4 x i64>* %a
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; ABS
|
|
;
|
|
|
|
define <4 x i8> @abs_v4i8(<4 x i8> %op1) #0 {
|
|
; CHECK-LABEL: abs_v4i8:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: adrp x8, .LCPI42_0
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.h, vl4
|
|
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI42_0]
|
|
; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h
|
|
; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h
|
|
; CHECK-NEXT: abs z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = call <4 x i8> @llvm.abs.v4i8(<4 x i8> %op1, i1 false)
|
|
ret <4 x i8> %res
|
|
}
|
|
|
|
define <8 x i8> @abs_v8i8(<8 x i8> %op1) #0 {
|
|
; CHECK-LABEL: abs_v8i8:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.b, vl8
|
|
; CHECK-NEXT: abs z0.b, p0/m, z0.b
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = call <8 x i8> @llvm.abs.v8i8(<8 x i8> %op1, i1 false)
|
|
ret <8 x i8> %res
|
|
}
|
|
|
|
define <16 x i8> @abs_v16i8(<16 x i8> %op1) #0 {
|
|
; CHECK-LABEL: abs_v16i8:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.b, vl16
|
|
; CHECK-NEXT: abs z0.b, p0/m, z0.b
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %op1, i1 false)
|
|
ret <16 x i8> %res
|
|
}
|
|
|
|
define void @abs_v32i8(<32 x i8>* %a) #0 {
|
|
; CHECK-LABEL: abs_v32i8:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.b, vl16
|
|
; CHECK-NEXT: abs z0.b, p0/m, z0.b
|
|
; CHECK-NEXT: abs z1.b, p0/m, z1.b
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <32 x i8>, <32 x i8>* %a
|
|
%res = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %op1, i1 false)
|
|
store <32 x i8> %res, <32 x i8>* %a
|
|
ret void
|
|
}
|
|
|
|
define <2 x i16> @abs_v2i16(<2 x i16> %op1) #0 {
|
|
; CHECK-LABEL: abs_v2i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: adrp x8, .LCPI46_0
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI46_0]
|
|
; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
|
|
; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s
|
|
; CHECK-NEXT: abs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %op1, i1 false)
|
|
ret <2 x i16> %res
|
|
}
|
|
|
|
define <4 x i16> @abs_v4i16(<4 x i16> %op1) #0 {
|
|
; CHECK-LABEL: abs_v4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.h, vl4
|
|
; CHECK-NEXT: abs z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %op1, i1 false)
|
|
ret <4 x i16> %res
|
|
}
|
|
|
|
define <8 x i16> @abs_v8i16(<8 x i16> %op1) #0 {
|
|
; CHECK-LABEL: abs_v8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.h, vl8
|
|
; CHECK-NEXT: abs z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %op1, i1 false)
|
|
ret <8 x i16> %res
|
|
}
|
|
|
|
define void @abs_v16i16(<16 x i16>* %a) #0 {
|
|
; CHECK-LABEL: abs_v16i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.h, vl8
|
|
; CHECK-NEXT: abs z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: abs z1.h, p0/m, z1.h
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x i16>, <16 x i16>* %a
|
|
%res = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %op1, i1 false)
|
|
store <16 x i16> %res, <16 x i16>* %a
|
|
ret void
|
|
}
|
|
|
|
define <2 x i32> @abs_v2i32(<2 x i32> %op1) #0 {
|
|
; CHECK-LABEL: abs_v2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: abs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %op1, i1 false)
|
|
ret <2 x i32> %res
|
|
}
|
|
|
|
define <4 x i32> @abs_v4i32(<4 x i32> %op1) #0 {
|
|
; CHECK-LABEL: abs_v4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: abs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %op1, i1 false)
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
define void @abs_v8i32(<8 x i32>* %a) #0 {
|
|
; CHECK-LABEL: abs_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: abs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: abs z1.s, p0/m, z1.s
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x i32>, <8 x i32>* %a
|
|
%res = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %op1, i1 false)
|
|
store <8 x i32> %res, <8 x i32>* %a
|
|
ret void
|
|
}
|
|
|
|
define <1 x i64> @abs_v1i64(<1 x i64> %op1) #0 {
|
|
; CHECK-LABEL: abs_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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|
; CHECK-NEXT: ptrue p0.d, vl1
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|
; CHECK-NEXT: abs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = call <1 x i64> @llvm.abs.v1i64(<1 x i64> %op1, i1 false)
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
define <2 x i64> @abs_v2i64(<2 x i64> %op1) #0 {
|
|
; CHECK-LABEL: abs_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: abs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %op1, i1 false)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @abs_v4i64(<4 x i64>* %a) #0 {
|
|
; CHECK-LABEL: abs_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: abs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: abs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <4 x i64>, <4 x i64>* %a
|
|
%res = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %op1, i1 false)
|
|
store <4 x i64> %res, <4 x i64>* %a
|
|
ret void
|
|
}
|
|
|
|
declare <4 x i8> @llvm.abs.v4i8(<4 x i8>, i1)
|
|
declare <8 x i8> @llvm.abs.v8i8(<8 x i8>, i1)
|
|
declare <16 x i8> @llvm.abs.v16i8(<16 x i8>, i1)
|
|
declare <32 x i8> @llvm.abs.v32i8(<32 x i8>, i1)
|
|
declare <4 x i16> @llvm.abs.v4i16(<4 x i16>, i1)
|
|
declare <2 x i16> @llvm.abs.v2i16(<2 x i16>, i1)
|
|
declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1)
|
|
declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1)
|
|
declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1)
|
|
declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
|
|
declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)
|
|
declare <1 x i64> @llvm.abs.v1i64(<1 x i64>, i1)
|
|
declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1)
|
|
declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)
|
|
|
|
|
|
attributes #0 = { "target-features"="+sve" }
|