forked from OSchip/llvm-project
1506 lines
47 KiB
LLVM
1506 lines
47 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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;
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; FCVTZU H -> H
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;
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define <4 x i16> @fcvtzu_v4f16_v4i16(<4 x half> %op1) #0 {
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; CHECK-LABEL: fcvtzu_v4f16_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = fptoui <4 x half> %op1 to <4 x i16>
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ret <4 x i16> %res
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}
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define void @fcvtzu_v8f16_v8i16(<8 x half>* %a, <8 x i16>* %b) #0 {
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; CHECK-LABEL: fcvtzu_v8f16_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%op1 = load <8 x half>, <8 x half>* %a
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%res = fptoui <8 x half> %op1 to <8 x i16>
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store <8 x i16> %res, <8 x i16>* %b
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ret void
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}
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define void @fcvtzu_v16f16_v16i16(<16 x half>* %a, <16 x i16>* %b) #0 {
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; CHECK-LABEL: fcvtzu_v16f16_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h
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; CHECK-NEXT: fcvtzu z1.h, p0/m, z1.h
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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%op1 = load <16 x half>, <16 x half>* %a
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%res = fptoui <16 x half> %op1 to <16 x i16>
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store <16 x i16> %res, <16 x i16>* %b
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ret void
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}
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;
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; FCVTZU H -> S
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;
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define <2 x i32> @fcvtzu_v2f16_v2i32(<2 x half> %op1) #0 {
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; CHECK-LABEL: fcvtzu_v2f16_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: uunpklo z0.s, z0.h
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = fptoui <2 x half> %op1 to <2 x i32>
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ret <2 x i32> %res
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}
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define <4 x i32> @fcvtzu_v4f16_v4i32(<4 x half> %op1) #0 {
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; CHECK-LABEL: fcvtzu_v4f16_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: uunpklo z0.s, z0.h
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = fptoui <4 x half> %op1 to <4 x i32>
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ret <4 x i32> %res
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}
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define void @fcvtzu_v8f16_v8i32(<8 x half>* %a, <8 x i32>* %b) #0 {
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; CHECK-LABEL: fcvtzu_v8f16_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: uunpklo z1.s, z0.h
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; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
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; CHECK-NEXT: uunpklo z0.s, z0.h
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; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.h
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
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; CHECK-NEXT: stp q1, q0, [x1]
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; CHECK-NEXT: ret
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%op1 = load <8 x half>, <8 x half>* %a
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%res = fptoui <8 x half> %op1 to <8 x i32>
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store <8 x i32> %res, <8 x i32>* %b
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ret void
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}
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define void @fcvtzu_v16f16_v16i32(<16 x half>* %a, <16 x i32>* %b) #0 {
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; CHECK-LABEL: fcvtzu_v16f16_v16i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: uunpklo z2.s, z0.h
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; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
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; CHECK-NEXT: uunpklo z0.s, z0.h
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; CHECK-NEXT: uunpklo z3.s, z1.h
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; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
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; CHECK-NEXT: uunpklo z1.s, z1.h
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; CHECK-NEXT: fcvtzu z3.s, p0/m, z3.h
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; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.h
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
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; CHECK-NEXT: stp q3, q1, [x1, #32]
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; CHECK-NEXT: movprfx z1, z2
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; CHECK-NEXT: fcvtzu z1.s, p0/m, z2.h
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; CHECK-NEXT: stp q1, q0, [x1]
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; CHECK-NEXT: ret
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%op1 = load <16 x half>, <16 x half>* %a
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%res = fptoui <16 x half> %op1 to <16 x i32>
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store <16 x i32> %res, <16 x i32>* %b
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ret void
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}
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;
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; FCVTZU H -> D
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;
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define <1 x i64> @fcvtzu_v1f16_v1i64(<1 x half> %op1) #0 {
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; CHECK-LABEL: fcvtzu_v1f16_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtzu x8, h0
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; CHECK-NEXT: fmov d0, x8
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; CHECK-NEXT: ret
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%res = fptoui <1 x half> %op1 to <1 x i64>
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ret <1 x i64> %res
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}
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define <2 x i64> @fcvtzu_v2f16_v2i64(<2 x half> %op1) #0 {
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; CHECK-LABEL: fcvtzu_v2f16_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: fcvtzu x8, h0
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; CHECK-NEXT: mov z0.h, z0.h[1]
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; CHECK-NEXT: fcvtzu x9, h0
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; CHECK-NEXT: stp x8, x9, [sp, #-16]!
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: ldr q0, [sp], #16
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; CHECK-NEXT: ret
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%res = fptoui <2 x half> %op1 to <2 x i64>
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ret <2 x i64> %res
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}
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define void @fcvtzu_v4f16_v4i64(<4 x half>* %a, <4 x i64>* %b) #0 {
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; CHECK-LABEL: fcvtzu_v4f16_v4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: mov z1.h, z0.h[1]
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; CHECK-NEXT: fcvtzu x8, h0
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; CHECK-NEXT: fcvtzu x9, h1
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; CHECK-NEXT: mov z1.h, z0.h[3]
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; CHECK-NEXT: mov z0.h, z0.h[2]
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; CHECK-NEXT: fcvtzu x10, h1
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; CHECK-NEXT: fcvtzu x11, h0
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; CHECK-NEXT: stp x8, x9, [sp, #-32]!
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: stp x11, x10, [sp, #16]
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; CHECK-NEXT: ldp q1, q0, [sp]
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; CHECK-NEXT: stp q1, q0, [x1]
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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%op1 = load <4 x half>, <4 x half>* %a
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%res = fptoui <4 x half> %op1 to <4 x i64>
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store <4 x i64> %res, <4 x i64>* %b
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ret void
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}
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define void @fcvtzu_v8f16_v8i64(<8 x half>* %a, <8 x i64>* %b) #0 {
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; CHECK-LABEL: fcvtzu_v8f16_v8i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #64
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: mov z1.h, z0.h[1]
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; CHECK-NEXT: fcvtzu x8, h0
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; CHECK-NEXT: fcvtzu x9, h1
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; CHECK-NEXT: mov z1.h, z0.h[3]
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; CHECK-NEXT: fcvtzu x10, h1
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; CHECK-NEXT: mov z1.h, z0.h[2]
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; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
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; CHECK-NEXT: fcvtzu x11, h1
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; CHECK-NEXT: mov z1.h, z0.h[1]
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; CHECK-NEXT: fcvtzu x12, h0
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; CHECK-NEXT: stp x8, x9, [sp, #32]
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; CHECK-NEXT: fcvtzu x8, h1
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; CHECK-NEXT: mov z1.h, z0.h[3]
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; CHECK-NEXT: mov z0.h, z0.h[2]
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; CHECK-NEXT: stp x11, x10, [sp, #48]
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; CHECK-NEXT: fcvtzu x9, h1
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; CHECK-NEXT: fcvtzu x10, h0
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; CHECK-NEXT: stp x12, x8, [sp]
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; CHECK-NEXT: ldp q3, q2, [sp, #32]
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; CHECK-NEXT: stp x10, x9, [sp, #16]
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; CHECK-NEXT: ldp q1, q0, [sp]
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; CHECK-NEXT: stp q3, q2, [x1]
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; CHECK-NEXT: stp q1, q0, [x1, #32]
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; CHECK-NEXT: add sp, sp, #64
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; CHECK-NEXT: ret
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%op1 = load <8 x half>, <8 x half>* %a
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%res = fptoui <8 x half> %op1 to <8 x i64>
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store <8 x i64> %res, <8 x i64>* %b
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ret void
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}
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define void @fcvtzu_v16f16_v16i64(<16 x half>* %a, <16 x i64>* %b) #0 {
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; CHECK-LABEL: fcvtzu_v16f16_v16i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #128
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; CHECK-NEXT: .cfi_def_cfa_offset 128
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: mov z2.h, z1.h[1]
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; CHECK-NEXT: mov z3.h, z1.h[3]
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; CHECK-NEXT: fcvtzu x9, h2
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; CHECK-NEXT: mov z2.h, z1.h[2]
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; CHECK-NEXT: fcvtzu x8, h1
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; CHECK-NEXT: fcvtzu x10, h3
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; CHECK-NEXT: fcvtzu x11, h2
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; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
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; CHECK-NEXT: fcvtzu x12, h1
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; CHECK-NEXT: mov z2.h, z1.h[1]
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; CHECK-NEXT: mov z3.h, z1.h[3]
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; CHECK-NEXT: mov z1.h, z1.h[2]
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; CHECK-NEXT: stp x8, x9, [sp, #32]
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; CHECK-NEXT: fcvtzu x9, h3
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; CHECK-NEXT: stp x11, x10, [sp, #48]
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; CHECK-NEXT: fcvtzu x10, h1
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; CHECK-NEXT: fcvtzu x8, h2
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; CHECK-NEXT: mov z1.h, z0.h[1]
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; CHECK-NEXT: stp x10, x9, [sp, #16]
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; CHECK-NEXT: fcvtzu x9, h1
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; CHECK-NEXT: mov z1.h, z0.h[3]
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; CHECK-NEXT: stp x12, x8, [sp]
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; CHECK-NEXT: fcvtzu x8, h0
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; CHECK-NEXT: fcvtzu x10, h1
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; CHECK-NEXT: mov z1.h, z0.h[2]
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; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
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; CHECK-NEXT: fcvtzu x11, h1
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; CHECK-NEXT: mov z1.h, z0.h[1]
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; CHECK-NEXT: stp x8, x9, [sp, #96]
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; CHECK-NEXT: fcvtzu x8, h0
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; CHECK-NEXT: fcvtzu x9, h1
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; CHECK-NEXT: mov z1.h, z0.h[3]
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; CHECK-NEXT: mov z0.h, z0.h[2]
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; CHECK-NEXT: stp x11, x10, [sp, #112]
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; CHECK-NEXT: fcvtzu x10, h1
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; CHECK-NEXT: fcvtzu x11, h0
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; CHECK-NEXT: stp x8, x9, [sp, #64]
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; CHECK-NEXT: ldp q0, q1, [sp, #32]
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; CHECK-NEXT: stp x11, x10, [sp, #80]
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; CHECK-NEXT: ldp q2, q3, [sp]
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; CHECK-NEXT: ldp q5, q4, [sp, #64]
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; CHECK-NEXT: ldp q7, q6, [sp, #96]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: stp q2, q3, [x1, #32]
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; CHECK-NEXT: stp q5, q4, [x1, #96]
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; CHECK-NEXT: stp q7, q6, [x1, #64]
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; CHECK-NEXT: add sp, sp, #128
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; CHECK-NEXT: ret
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%op1 = load <16 x half>, <16 x half>* %a
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%res = fptoui <16 x half> %op1 to <16 x i64>
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store <16 x i64> %res, <16 x i64>* %b
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ret void
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}
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;
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; FCVTZU S -> H
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;
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define <2 x i16> @fcvtzu_v2f32_v2i16(<2 x float> %op1) #0 {
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; CHECK-LABEL: fcvtzu_v2f32_v2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = fptoui <2 x float> %op1 to <2 x i16>
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ret <2 x i16> %res
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}
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define <4 x i16> @fcvtzu_v4f32_v4i16(<4 x float> %op1) #0 {
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; CHECK-LABEL: fcvtzu_v4f32_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = fptoui <4 x float> %op1 to <4 x i16>
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ret <4 x i16> %res
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}
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define <8 x i16> @fcvtzu_v8f32_v8i16(<8 x float>* %a) #0 {
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; CHECK-LABEL: fcvtzu_v8f32_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h
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; CHECK-NEXT: uzp1 z0.h, z1.h, z1.h
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; CHECK-NEXT: splice z0.h, p0, z0.h, z2.h
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%op1 = load <8 x float>, <8 x float>* %a
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%res = fptoui <8 x float> %op1 to <8 x i16>
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ret <8 x i16> %res
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}
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define void @fcvtzu_v16f32_v16i16(<16 x float>* %a, <16 x i16>* %b) #0 {
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; CHECK-LABEL: fcvtzu_v16f32_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: ptrue p1.h, vl4
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
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; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
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; CHECK-NEXT: ldp q3, q2, [x0, #32]
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; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s
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; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
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; CHECK-NEXT: splice z0.h, p1, z0.h, z1.h
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; CHECK-NEXT: fcvtzu z3.s, p0/m, z3.s
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; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h
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; CHECK-NEXT: fcvtzu z2.s, p0/m, z2.s
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; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h
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; CHECK-NEXT: splice z3.h, p1, z3.h, z2.h
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; CHECK-NEXT: stp q0, q3, [x1]
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; CHECK-NEXT: ret
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%op1 = load <16 x float>, <16 x float>* %a
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%res = fptoui <16 x float> %op1 to <16 x i16>
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store <16 x i16> %res, <16 x i16>* %b
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ret void
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}
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;
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; FCVTZU S -> S
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;
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define <2 x i32> @fcvtzu_v2f32_v2i32(<2 x float> %op1) #0 {
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; CHECK-LABEL: fcvtzu_v2f32_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptoui <2 x float> %op1 to <2 x i32>
|
|
ret <2 x i32> %res
|
|
}
|
|
|
|
define <4 x i32> @fcvtzu_v4f32_v4i32(<4 x float> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzu_v4f32_v4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptoui <4 x float> %op1 to <4 x i32>
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
define void @fcvtzu_v8f32_v8i32(<8 x float>* %a, <8 x i32>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzu_v8f32_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x float>, <8 x float>* %a
|
|
%res = fptoui <8 x float> %op1 to <8 x i32>
|
|
store <8 x i32> %res, <8 x i32>* %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZU S -> D
|
|
;
|
|
|
|
define <1 x i64> @fcvtzu_v1f32_v1i64(<1 x float> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzu_v1f32_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptoui <1 x float> %op1 to <1 x i64>
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
define <2 x i64> @fcvtzu_v2f32_v2i64(<2 x float> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzu_v2f32_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptoui <2 x float> %op1 to <2 x i64>
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @fcvtzu_v4f32_v4i64(<4 x float>* %a, <4 x i64>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzu_v4f32_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: uunpklo z1.d, z0.s
|
|
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.s
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: stp q1, q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <4 x float>, <4 x float>* %a
|
|
%res = fptoui <4 x float> %op1 to <4 x i64>
|
|
store <4 x i64> %res, <4 x i64>* %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzu_v8f32_v8i64(<8 x float>* %a, <8 x i64>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzu_v8f32_v8i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: uunpklo z2.d, z0.s
|
|
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: uunpklo z3.d, z1.s
|
|
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
|
|
; CHECK-NEXT: uunpklo z1.d, z1.s
|
|
; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.s
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.s
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: stp q3, q1, [x1, #32]
|
|
; CHECK-NEXT: movprfx z1, z2
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z2.s
|
|
; CHECK-NEXT: stp q1, q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x float>, <8 x float>* %a
|
|
%res = fptoui <8 x float> %op1 to <8 x i64>
|
|
store <8 x i64> %res, <8 x i64>* %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZU D -> H
|
|
;
|
|
|
|
define <1 x i16> @fcvtzu_v1f64_v1i16(<1 x double> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzu_v1f64_v1i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzs w8, d0
|
|
; CHECK-NEXT: fmov s0, w8
|
|
; CHECK-NEXT: ret
|
|
%res = fptoui <1 x double> %op1 to <1 x i16>
|
|
ret <1 x i16> %res
|
|
}
|
|
|
|
define <2 x i16> @fcvtzu_v2f64_v2i16(<2 x double> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzu_v2f64_v2i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptoui <2 x double> %op1 to <2 x i16>
|
|
ret <2 x i16> %res
|
|
}
|
|
|
|
define <4 x i16> @fcvtzu_v4f64_v4i16(<4 x double>* %a) #0 {
|
|
; CHECK-LABEL: fcvtzu_v4f64_v4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: sub sp, sp, #16
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: fmov w9, s1
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: mov z1.s, z1.s[1]
|
|
; CHECK-NEXT: fmov w8, s0
|
|
; CHECK-NEXT: mov z0.s, z0.s[1]
|
|
; CHECK-NEXT: fmov w10, s0
|
|
; CHECK-NEXT: strh w9, [sp, #8]
|
|
; CHECK-NEXT: strh w8, [sp, #12]
|
|
; CHECK-NEXT: fmov w8, s1
|
|
; CHECK-NEXT: strh w10, [sp, #14]
|
|
; CHECK-NEXT: strh w8, [sp, #10]
|
|
; CHECK-NEXT: ldr d0, [sp, #8]
|
|
; CHECK-NEXT: add sp, sp, #16
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <4 x double>, <4 x double>* %a
|
|
%res = fptoui <4 x double> %op1 to <4 x i16>
|
|
ret <4 x i16> %res
|
|
}
|
|
|
|
define <8 x i16> @fcvtzu_v8f64_v8i16(<8 x double>* %a) #0 {
|
|
; CHECK-LABEL: fcvtzu_v8f64_v8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: sub sp, sp, #16
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
|
; CHECK-NEXT: ldp q0, q1, [x0, #32]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: ldp q3, q2, [x0]
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: fmov w9, s0
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: fmov w8, s1
|
|
; CHECK-NEXT: mov z4.s, z1.s[1]
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
|
|
; CHECK-NEXT: strh w9, [sp, #8]
|
|
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
|
|
; CHECK-NEXT: fmov w9, s4
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: strh w8, [sp, #12]
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: fmov w8, s3
|
|
; CHECK-NEXT: fmov w10, s2
|
|
; CHECK-NEXT: mov z1.s, z0.s[1]
|
|
; CHECK-NEXT: mov z0.s, z2.s[1]
|
|
; CHECK-NEXT: mov z2.s, z3.s[1]
|
|
; CHECK-NEXT: strh w8, [sp]
|
|
; CHECK-NEXT: fmov w8, s0
|
|
; CHECK-NEXT: strh w10, [sp, #4]
|
|
; CHECK-NEXT: fmov w10, s1
|
|
; CHECK-NEXT: strh w9, [sp, #14]
|
|
; CHECK-NEXT: fmov w9, s2
|
|
; CHECK-NEXT: strh w8, [sp, #6]
|
|
; CHECK-NEXT: strh w10, [sp, #10]
|
|
; CHECK-NEXT: strh w9, [sp, #2]
|
|
; CHECK-NEXT: ldr q0, [sp], #16
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x double>, <8 x double>* %a
|
|
%res = fptoui <8 x double> %op1 to <8 x i16>
|
|
ret <8 x i16> %res
|
|
}
|
|
|
|
define void @fcvtzu_v16f64_v16i16(<16 x double>* %a, <16 x i16>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzu_v16f64_v16i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: sub sp, sp, #32
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-NEXT: ldp q2, q3, [x0, #32]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: ldp q4, q5, [x0]
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
|
|
; CHECK-NEXT: fmov w9, s2
|
|
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
|
|
; CHECK-NEXT: fmov w8, s3
|
|
; CHECK-NEXT: mov z6.s, z3.s[1]
|
|
; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
|
|
; CHECK-NEXT: mov z3.s, z2.s[1]
|
|
; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s
|
|
; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
|
|
; CHECK-NEXT: ldp q0, q1, [x0, #64]
|
|
; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s
|
|
; CHECK-NEXT: fmov w10, s5
|
|
; CHECK-NEXT: mov z5.s, z5.s[1]
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: ldp q2, q7, [x0, #96]
|
|
; CHECK-NEXT: strh w8, [sp, #12]
|
|
; CHECK-NEXT: fmov w8, s4
|
|
; CHECK-NEXT: strh w9, [sp, #8]
|
|
; CHECK-NEXT: fmov w9, s6
|
|
; CHECK-NEXT: strh w10, [sp, #4]
|
|
; CHECK-NEXT: mov z4.s, z4.s[1]
|
|
; CHECK-NEXT: strh w8, [sp]
|
|
; CHECK-NEXT: fmov w8, s3
|
|
; CHECK-NEXT: strh w9, [sp, #14]
|
|
; CHECK-NEXT: movprfx z3, z7
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z7.d
|
|
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: strh w8, [sp, #10]
|
|
; CHECK-NEXT: fmov w8, s3
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: fmov w9, s5
|
|
; CHECK-NEXT: fmov w10, s4
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: strh w8, [sp, #28]
|
|
; CHECK-NEXT: fmov w8, s2
|
|
; CHECK-NEXT: mov z3.s, z3.s[1]
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: strh w9, [sp, #6]
|
|
; CHECK-NEXT: fmov w9, s1
|
|
; CHECK-NEXT: strh w10, [sp, #2]
|
|
; CHECK-NEXT: fmov w10, s0
|
|
; CHECK-NEXT: strh w8, [sp, #24]
|
|
; CHECK-NEXT: fmov w8, s3
|
|
; CHECK-NEXT: mov z4.s, z2.s[1]
|
|
; CHECK-NEXT: mov z2.s, z1.s[1]
|
|
; CHECK-NEXT: mov z1.s, z0.s[1]
|
|
; CHECK-NEXT: strh w9, [sp, #20]
|
|
; CHECK-NEXT: fmov w9, s4
|
|
; CHECK-NEXT: strh w10, [sp, #16]
|
|
; CHECK-NEXT: fmov w10, s2
|
|
; CHECK-NEXT: strh w8, [sp, #30]
|
|
; CHECK-NEXT: fmov w8, s1
|
|
; CHECK-NEXT: strh w9, [sp, #26]
|
|
; CHECK-NEXT: strh w10, [sp, #22]
|
|
; CHECK-NEXT: strh w8, [sp, #18]
|
|
; CHECK-NEXT: ldp q1, q0, [sp]
|
|
; CHECK-NEXT: stp q1, q0, [x1]
|
|
; CHECK-NEXT: add sp, sp, #32
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x double>, <16 x double>* %a
|
|
%res = fptoui <16 x double> %op1 to <16 x i16>
|
|
store <16 x i16> %res, <16 x i16>* %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZU D -> S
|
|
;
|
|
|
|
define <1 x i32> @fcvtzu_v1f64_v1i32(<1 x double> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzu_v1f64_v1i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptoui <1 x double> %op1 to <1 x i32>
|
|
ret <1 x i32> %res
|
|
}
|
|
|
|
define <2 x i32> @fcvtzu_v2f64_v2i32(<2 x double> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzu_v2f64_v2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptoui <2 x double> %op1 to <2 x i32>
|
|
ret <2 x i32> %res
|
|
}
|
|
|
|
define <4 x i32> @fcvtzu_v4f64_v4i32(<4 x double>* %a) #0 {
|
|
; CHECK-LABEL: fcvtzu_v4f64_v4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: uzp1 z2.s, z0.s, z0.s
|
|
; CHECK-NEXT: uzp1 z0.s, z1.s, z1.s
|
|
; CHECK-NEXT: splice z0.s, p0, z0.s, z2.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <4 x double>, <4 x double>* %a
|
|
%res = fptoui <4 x double> %op1 to <4 x i32>
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
define void @fcvtzu_v8f64_v8i32(<8 x double>* %a, <8 x i32>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzu_v8f64_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: ptrue p1.s, vl2
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: ldp q3, q2, [x0, #32]
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: splice z0.s, p1, z0.s, z1.s
|
|
; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.d
|
|
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
|
|
; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: splice z3.s, p1, z3.s, z2.s
|
|
; CHECK-NEXT: stp q0, q3, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x double>, <8 x double>* %a
|
|
%res = fptoui <8 x double> %op1 to <8 x i32>
|
|
store <8 x i32> %res, <8 x i32>* %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZU D -> D
|
|
;
|
|
|
|
define <1 x i64> @fcvtzu_v1f64_v1i64(<1 x double> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzu_v1f64_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzu x8, d0
|
|
; CHECK-NEXT: fmov d0, x8
|
|
; CHECK-NEXT: ret
|
|
%res = fptoui <1 x double> %op1 to <1 x i64>
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
define <2 x i64> @fcvtzu_v2f64_v2i64(<2 x double> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzu_v2f64_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptoui <2 x double> %op1 to <2 x i64>
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @fcvtzu_v4f64_v4i64(<4 x double>* %a, <4 x i64>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzu_v4f64_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <4 x double>, <4 x double>* %a
|
|
%res = fptoui <4 x double> %op1 to <4 x i64>
|
|
store <4 x i64> %res, <4 x i64>* %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS H -> H
|
|
;
|
|
|
|
define <4 x i16> @fcvtzs_v4f16_v4i16(<4 x half> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v4f16_v4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.h, vl4
|
|
; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <4 x half> %op1 to <4 x i16>
|
|
ret <4 x i16> %res
|
|
}
|
|
|
|
define void @fcvtzs_v8f16_v8i16(<8 x half>* %a, <8 x i16>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzs_v8f16_v8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.h, vl8
|
|
; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: str q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x half>, <8 x half>* %a
|
|
%res = fptosi <8 x half> %op1 to <8 x i16>
|
|
store <8 x i16> %res, <8 x i16>* %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzs_v16f16_v16i16(<16 x half>* %a, <16 x i16>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzs_v16f16_v16i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.h, vl8
|
|
; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: fcvtzs z1.h, p0/m, z1.h
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, <16 x half>* %a
|
|
%res = fptosi <16 x half> %op1 to <16 x i16>
|
|
store <16 x i16> %res, <16 x i16>* %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS H -> S
|
|
;
|
|
|
|
define <2 x i32> @fcvtzs_v2f16_v2i32(<2 x half> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v2f16_v2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <2 x half> %op1 to <2 x i32>
|
|
ret <2 x i32> %res
|
|
}
|
|
|
|
define <4 x i32> @fcvtzs_v4f16_v4i32(<4 x half> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v4f16_v4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <4 x half> %op1 to <4 x i32>
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
define void @fcvtzs_v8f16_v8i32(<8 x half>* %a, <8 x i32>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzs_v8f16_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: uunpklo z1.s, z0.h
|
|
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.h
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
|
|
; CHECK-NEXT: stp q1, q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x half>, <8 x half>* %a
|
|
%res = fptosi <8 x half> %op1 to <8 x i32>
|
|
store <8 x i32> %res, <8 x i32>* %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzs_v16f16_v16i32(<16 x half>* %a, <16 x i32>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzs_v16f16_v16i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: uunpklo z2.s, z0.h
|
|
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: uunpklo z3.s, z1.h
|
|
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: fcvtzs z3.s, p0/m, z3.h
|
|
; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.h
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
|
|
; CHECK-NEXT: stp q3, q1, [x1, #32]
|
|
; CHECK-NEXT: movprfx z1, z2
|
|
; CHECK-NEXT: fcvtzs z1.s, p0/m, z2.h
|
|
; CHECK-NEXT: stp q1, q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, <16 x half>* %a
|
|
%res = fptosi <16 x half> %op1 to <16 x i32>
|
|
store <16 x i32> %res, <16 x i32>* %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS H -> D
|
|
;
|
|
|
|
define <1 x i64> @fcvtzs_v1f16_v1i64(<1 x half> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v1f16_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: fcvtzs x8, h0
|
|
; CHECK-NEXT: fmov d0, x8
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <1 x half> %op1 to <1 x i64>
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
; v2f16 is not legal for NEON, so use SVE
|
|
define <2 x i64> @fcvtzs_v2f16_v2i64(<2 x half> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v2f16_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzs x8, h0
|
|
; CHECK-NEXT: mov z0.h, z0.h[1]
|
|
; CHECK-NEXT: fcvtzs x9, h0
|
|
; CHECK-NEXT: stp x8, x9, [sp, #-16]!
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
|
; CHECK-NEXT: ldr q0, [sp], #16
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <2 x half> %op1 to <2 x i64>
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @fcvtzs_v4f16_v4i64(<4 x half>* %a, <4 x i64>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzs_v4f16_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr d0, [x0]
|
|
; CHECK-NEXT: mov z1.h, z0.h[1]
|
|
; CHECK-NEXT: fcvtzs x8, h0
|
|
; CHECK-NEXT: fcvtzs x9, h1
|
|
; CHECK-NEXT: mov z1.h, z0.h[3]
|
|
; CHECK-NEXT: mov z0.h, z0.h[2]
|
|
; CHECK-NEXT: fcvtzs x10, h1
|
|
; CHECK-NEXT: fcvtzs x11, h0
|
|
; CHECK-NEXT: stp x8, x9, [sp, #-32]!
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-NEXT: stp x11, x10, [sp, #16]
|
|
; CHECK-NEXT: ldp q1, q0, [sp]
|
|
; CHECK-NEXT: stp q1, q0, [x1]
|
|
; CHECK-NEXT: add sp, sp, #32
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <4 x half>, <4 x half>* %a
|
|
%res = fptosi <4 x half> %op1 to <4 x i64>
|
|
store <4 x i64> %res, <4 x i64>* %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzs_v8f16_v8i64(<8 x half>* %a, <8 x i64>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzs_v8f16_v8i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: sub sp, sp, #64
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 64
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: mov z1.h, z0.h[1]
|
|
; CHECK-NEXT: fcvtzs x8, h0
|
|
; CHECK-NEXT: fcvtzs x9, h1
|
|
; CHECK-NEXT: mov z1.h, z0.h[3]
|
|
; CHECK-NEXT: fcvtzs x10, h1
|
|
; CHECK-NEXT: mov z1.h, z0.h[2]
|
|
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
|
|
; CHECK-NEXT: fcvtzs x11, h1
|
|
; CHECK-NEXT: mov z1.h, z0.h[1]
|
|
; CHECK-NEXT: fcvtzs x12, h0
|
|
; CHECK-NEXT: stp x8, x9, [sp, #32]
|
|
; CHECK-NEXT: fcvtzs x8, h1
|
|
; CHECK-NEXT: mov z1.h, z0.h[3]
|
|
; CHECK-NEXT: mov z0.h, z0.h[2]
|
|
; CHECK-NEXT: stp x11, x10, [sp, #48]
|
|
; CHECK-NEXT: fcvtzs x9, h1
|
|
; CHECK-NEXT: fcvtzs x10, h0
|
|
; CHECK-NEXT: stp x12, x8, [sp]
|
|
; CHECK-NEXT: ldp q3, q2, [sp, #32]
|
|
; CHECK-NEXT: stp x10, x9, [sp, #16]
|
|
; CHECK-NEXT: ldp q1, q0, [sp]
|
|
; CHECK-NEXT: stp q3, q2, [x1]
|
|
; CHECK-NEXT: stp q1, q0, [x1, #32]
|
|
; CHECK-NEXT: add sp, sp, #64
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x half>, <8 x half>* %a
|
|
%res = fptosi <8 x half> %op1 to <8 x i64>
|
|
store <8 x i64> %res, <8 x i64>* %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzs_v16f16_v16i64(<16 x half>* %a, <16 x i64>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzs_v16f16_v16i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: sub sp, sp, #128
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 128
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: mov z2.h, z1.h[1]
|
|
; CHECK-NEXT: mov z3.h, z1.h[3]
|
|
; CHECK-NEXT: fcvtzs x9, h2
|
|
; CHECK-NEXT: mov z2.h, z1.h[2]
|
|
; CHECK-NEXT: fcvtzs x8, h1
|
|
; CHECK-NEXT: fcvtzs x10, h3
|
|
; CHECK-NEXT: fcvtzs x11, h2
|
|
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
|
|
; CHECK-NEXT: fcvtzs x12, h1
|
|
; CHECK-NEXT: mov z2.h, z1.h[1]
|
|
; CHECK-NEXT: mov z3.h, z1.h[3]
|
|
; CHECK-NEXT: mov z1.h, z1.h[2]
|
|
; CHECK-NEXT: stp x8, x9, [sp, #32]
|
|
; CHECK-NEXT: fcvtzs x9, h3
|
|
; CHECK-NEXT: stp x11, x10, [sp, #48]
|
|
; CHECK-NEXT: fcvtzs x10, h1
|
|
; CHECK-NEXT: fcvtzs x8, h2
|
|
; CHECK-NEXT: mov z1.h, z0.h[1]
|
|
; CHECK-NEXT: stp x10, x9, [sp, #16]
|
|
; CHECK-NEXT: fcvtzs x9, h1
|
|
; CHECK-NEXT: mov z1.h, z0.h[3]
|
|
; CHECK-NEXT: stp x12, x8, [sp]
|
|
; CHECK-NEXT: fcvtzs x8, h0
|
|
; CHECK-NEXT: fcvtzs x10, h1
|
|
; CHECK-NEXT: mov z1.h, z0.h[2]
|
|
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
|
|
; CHECK-NEXT: fcvtzs x11, h1
|
|
; CHECK-NEXT: mov z1.h, z0.h[1]
|
|
; CHECK-NEXT: stp x8, x9, [sp, #96]
|
|
; CHECK-NEXT: fcvtzs x8, h0
|
|
; CHECK-NEXT: fcvtzs x9, h1
|
|
; CHECK-NEXT: mov z1.h, z0.h[3]
|
|
; CHECK-NEXT: mov z0.h, z0.h[2]
|
|
; CHECK-NEXT: stp x11, x10, [sp, #112]
|
|
; CHECK-NEXT: fcvtzs x10, h1
|
|
; CHECK-NEXT: fcvtzs x11, h0
|
|
; CHECK-NEXT: stp x8, x9, [sp, #64]
|
|
; CHECK-NEXT: ldp q0, q1, [sp, #32]
|
|
; CHECK-NEXT: stp x11, x10, [sp, #80]
|
|
; CHECK-NEXT: ldp q2, q3, [sp]
|
|
; CHECK-NEXT: ldp q5, q4, [sp, #64]
|
|
; CHECK-NEXT: ldp q7, q6, [sp, #96]
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: stp q2, q3, [x1, #32]
|
|
; CHECK-NEXT: stp q5, q4, [x1, #96]
|
|
; CHECK-NEXT: stp q7, q6, [x1, #64]
|
|
; CHECK-NEXT: add sp, sp, #128
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, <16 x half>* %a
|
|
%res = fptosi <16 x half> %op1 to <16 x i64>
|
|
store <16 x i64> %res, <16 x i64>* %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS S -> H
|
|
;
|
|
|
|
define <2 x i16> @fcvtzs_v2f32_v2i16(<2 x float> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v2f32_v2i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <2 x float> %op1 to <2 x i16>
|
|
ret <2 x i16> %res
|
|
}
|
|
|
|
define <4 x i16> @fcvtzs_v4f32_v4i16(<4 x float> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v4f32_v4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <4 x float> %op1 to <4 x i16>
|
|
ret <4 x i16> %res
|
|
}
|
|
|
|
define <8 x i16> @fcvtzs_v8f32_v8i16(<8 x float>* %a) #0 {
|
|
; CHECK-LABEL: fcvtzs_v8f32_v8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: ptrue p0.h, vl4
|
|
; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h
|
|
; CHECK-NEXT: uzp1 z0.h, z1.h, z1.h
|
|
; CHECK-NEXT: splice z0.h, p0, z0.h, z2.h
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x float>, <8 x float>* %a
|
|
%res = fptosi <8 x float> %op1 to <8 x i16>
|
|
ret <8 x i16> %res
|
|
}
|
|
|
|
define void @fcvtzs_v16f32_v16i16(<16 x float>* %a, <16 x i16>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzs_v16f32_v16i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: ptrue p1.h, vl4
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; CHECK-NEXT: ldp q3, q2, [x0, #32]
|
|
; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
|
|
; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
|
|
; CHECK-NEXT: splice z0.h, p1, z0.h, z1.h
|
|
; CHECK-NEXT: fcvtzs z3.s, p0/m, z3.s
|
|
; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h
|
|
; CHECK-NEXT: fcvtzs z2.s, p0/m, z2.s
|
|
; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h
|
|
; CHECK-NEXT: splice z3.h, p1, z3.h, z2.h
|
|
; CHECK-NEXT: stp q0, q3, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x float>, <16 x float>* %a
|
|
%res = fptosi <16 x float> %op1 to <16 x i16>
|
|
store <16 x i16> %res, <16 x i16>* %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS S -> S
|
|
;
|
|
|
|
define <2 x i32> @fcvtzs_v2f32_v2i32(<2 x float> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v2f32_v2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <2 x float> %op1 to <2 x i32>
|
|
ret <2 x i32> %res
|
|
}
|
|
|
|
define <4 x i32> @fcvtzs_v4f32_v4i32(<4 x float> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v4f32_v4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <4 x float> %op1 to <4 x i32>
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
define void @fcvtzs_v8f32_v8i32(<8 x float>* %a, <8 x i32>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzs_v8f32_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x float>, <8 x float>* %a
|
|
%res = fptosi <8 x float> %op1 to <8 x i32>
|
|
store <8 x i32> %res, <8 x i32>* %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS S -> D
|
|
;
|
|
|
|
define <1 x i64> @fcvtzs_v1f32_v1i64(<1 x float> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v1f32_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <1 x float> %op1 to <1 x i64>
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
define <2 x i64> @fcvtzs_v2f32_v2i64(<2 x float> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v2f32_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <2 x float> %op1 to <2 x i64>
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @fcvtzs_v4f32_v4i64(<4 x float>* %a, <4 x i64>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzs_v4f32_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: uunpklo z1.d, z0.s
|
|
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.s
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: stp q1, q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <4 x float>, <4 x float>* %a
|
|
%res = fptosi <4 x float> %op1 to <4 x i64>
|
|
store <4 x i64> %res, <4 x i64>* %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzs_v8f32_v8i64(<8 x float>* %a, <8 x i64>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzs_v8f32_v8i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: uunpklo z2.d, z0.s
|
|
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: uunpklo z3.d, z1.s
|
|
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
|
|
; CHECK-NEXT: uunpklo z1.d, z1.s
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.s
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.s
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: stp q3, q1, [x1, #32]
|
|
; CHECK-NEXT: movprfx z1, z2
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.s
|
|
; CHECK-NEXT: stp q1, q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x float>, <8 x float>* %a
|
|
%res = fptosi <8 x float> %op1 to <8 x i64>
|
|
store <8 x i64> %res, <8 x i64>* %b
|
|
ret void
|
|
}
|
|
|
|
|
|
;
|
|
; FCVTZS D -> H
|
|
;
|
|
|
|
; v1f64 is perfered to be widened to v4f64, so use SVE
|
|
define <1 x i16> @fcvtzs_v1f64_v1i16(<1 x double> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v1f64_v1i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzs w8, d0
|
|
; CHECK-NEXT: fmov s0, w8
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <1 x double> %op1 to <1 x i16>
|
|
ret <1 x i16> %res
|
|
}
|
|
|
|
define <2 x i16> @fcvtzs_v2f64_v2i16(<2 x double> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v2f64_v2i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <2 x double> %op1 to <2 x i16>
|
|
ret <2 x i16> %res
|
|
}
|
|
|
|
define <4 x i16> @fcvtzs_v4f64_v4i16(<4 x double>* %a) #0 {
|
|
; CHECK-LABEL: fcvtzs_v4f64_v4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: sub sp, sp, #16
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: fmov w9, s1
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: mov z1.s, z1.s[1]
|
|
; CHECK-NEXT: fmov w8, s0
|
|
; CHECK-NEXT: mov z0.s, z0.s[1]
|
|
; CHECK-NEXT: fmov w10, s0
|
|
; CHECK-NEXT: strh w9, [sp, #8]
|
|
; CHECK-NEXT: strh w8, [sp, #12]
|
|
; CHECK-NEXT: fmov w8, s1
|
|
; CHECK-NEXT: strh w10, [sp, #14]
|
|
; CHECK-NEXT: strh w8, [sp, #10]
|
|
; CHECK-NEXT: ldr d0, [sp, #8]
|
|
; CHECK-NEXT: add sp, sp, #16
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <4 x double>, <4 x double>* %a
|
|
%res = fptosi <4 x double> %op1 to <4 x i16>
|
|
ret <4 x i16> %res
|
|
}
|
|
|
|
define <8 x i16> @fcvtzs_v8f64_v8i16(<8 x double>* %a) #0 {
|
|
; CHECK-LABEL: fcvtzs_v8f64_v8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: sub sp, sp, #16
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
|
; CHECK-NEXT: ldp q0, q1, [x0, #32]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: ldp q3, q2, [x0]
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: fmov w9, s0
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: fmov w8, s1
|
|
; CHECK-NEXT: mov z4.s, z1.s[1]
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
|
|
; CHECK-NEXT: strh w9, [sp, #8]
|
|
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
|
|
; CHECK-NEXT: fmov w9, s4
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: strh w8, [sp, #12]
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: fmov w8, s3
|
|
; CHECK-NEXT: fmov w10, s2
|
|
; CHECK-NEXT: mov z1.s, z0.s[1]
|
|
; CHECK-NEXT: mov z0.s, z2.s[1]
|
|
; CHECK-NEXT: mov z2.s, z3.s[1]
|
|
; CHECK-NEXT: strh w8, [sp]
|
|
; CHECK-NEXT: fmov w8, s0
|
|
; CHECK-NEXT: strh w10, [sp, #4]
|
|
; CHECK-NEXT: fmov w10, s1
|
|
; CHECK-NEXT: strh w9, [sp, #14]
|
|
; CHECK-NEXT: fmov w9, s2
|
|
; CHECK-NEXT: strh w8, [sp, #6]
|
|
; CHECK-NEXT: strh w10, [sp, #10]
|
|
; CHECK-NEXT: strh w9, [sp, #2]
|
|
; CHECK-NEXT: ldr q0, [sp], #16
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x double>, <8 x double>* %a
|
|
%res = fptosi <8 x double> %op1 to <8 x i16>
|
|
ret <8 x i16> %res
|
|
}
|
|
|
|
define void @fcvtzs_v16f64_v16i16(<16 x double>* %a, <16 x i16>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzs_v16f64_v16i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: sub sp, sp, #32
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-NEXT: ldp q2, q3, [x0, #32]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: ldp q4, q5, [x0]
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
|
|
; CHECK-NEXT: fmov w9, s2
|
|
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
|
|
; CHECK-NEXT: fmov w8, s3
|
|
; CHECK-NEXT: mov z6.s, z3.s[1]
|
|
; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
|
|
; CHECK-NEXT: mov z3.s, z2.s[1]
|
|
; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s
|
|
; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
|
|
; CHECK-NEXT: ldp q0, q1, [x0, #64]
|
|
; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s
|
|
; CHECK-NEXT: fmov w10, s5
|
|
; CHECK-NEXT: mov z5.s, z5.s[1]
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: ldp q2, q7, [x0, #96]
|
|
; CHECK-NEXT: strh w8, [sp, #12]
|
|
; CHECK-NEXT: fmov w8, s4
|
|
; CHECK-NEXT: strh w9, [sp, #8]
|
|
; CHECK-NEXT: fmov w9, s6
|
|
; CHECK-NEXT: strh w10, [sp, #4]
|
|
; CHECK-NEXT: mov z4.s, z4.s[1]
|
|
; CHECK-NEXT: strh w8, [sp]
|
|
; CHECK-NEXT: fmov w8, s3
|
|
; CHECK-NEXT: strh w9, [sp, #14]
|
|
; CHECK-NEXT: movprfx z3, z7
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z7.d
|
|
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: strh w8, [sp, #10]
|
|
; CHECK-NEXT: fmov w8, s3
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: fmov w9, s5
|
|
; CHECK-NEXT: fmov w10, s4
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: strh w8, [sp, #28]
|
|
; CHECK-NEXT: fmov w8, s2
|
|
; CHECK-NEXT: mov z3.s, z3.s[1]
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: strh w9, [sp, #6]
|
|
; CHECK-NEXT: fmov w9, s1
|
|
; CHECK-NEXT: strh w10, [sp, #2]
|
|
; CHECK-NEXT: fmov w10, s0
|
|
; CHECK-NEXT: strh w8, [sp, #24]
|
|
; CHECK-NEXT: fmov w8, s3
|
|
; CHECK-NEXT: mov z4.s, z2.s[1]
|
|
; CHECK-NEXT: mov z2.s, z1.s[1]
|
|
; CHECK-NEXT: mov z1.s, z0.s[1]
|
|
; CHECK-NEXT: strh w9, [sp, #20]
|
|
; CHECK-NEXT: fmov w9, s4
|
|
; CHECK-NEXT: strh w10, [sp, #16]
|
|
; CHECK-NEXT: fmov w10, s2
|
|
; CHECK-NEXT: strh w8, [sp, #30]
|
|
; CHECK-NEXT: fmov w8, s1
|
|
; CHECK-NEXT: strh w9, [sp, #26]
|
|
; CHECK-NEXT: strh w10, [sp, #22]
|
|
; CHECK-NEXT: strh w8, [sp, #18]
|
|
; CHECK-NEXT: ldp q1, q0, [sp]
|
|
; CHECK-NEXT: stp q1, q0, [x1]
|
|
; CHECK-NEXT: add sp, sp, #32
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x double>, <16 x double>* %a
|
|
%res = fptosi <16 x double> %op1 to <16 x i16>
|
|
store <16 x i16> %res, <16 x i16>* %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS D -> S
|
|
;
|
|
|
|
define <1 x i32> @fcvtzs_v1f64_v1i32(<1 x double> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v1f64_v1i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <1 x double> %op1 to <1 x i32>
|
|
ret <1 x i32> %res
|
|
}
|
|
|
|
define <2 x i32> @fcvtzs_v2f64_v2i32(<2 x double> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v2f64_v2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <2 x double> %op1 to <2 x i32>
|
|
ret <2 x i32> %res
|
|
}
|
|
|
|
define <4 x i32> @fcvtzs_v4f64_v4i32(<4 x double>* %a) #0 {
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; CHECK-LABEL: fcvtzs_v4f64_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: uzp1 z2.s, z0.s, z0.s
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; CHECK-NEXT: uzp1 z0.s, z1.s, z1.s
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; CHECK-NEXT: splice z0.s, p0, z0.s, z2.s
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%op1 = load <4 x double>, <4 x double>* %a
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%res = fptosi <4 x double> %op1 to <4 x i32>
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ret <4 x i32> %res
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}
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define void @fcvtzs_v8f64_v8i32(<8 x double>* %a, <8 x i32>* %b) #0 {
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; CHECK-LABEL: fcvtzs_v8f64_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: ptrue p1.s, vl2
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; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
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; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
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; CHECK-NEXT: ldp q3, q2, [x0, #32]
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; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
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; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
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|
; CHECK-NEXT: splice z0.s, p1, z0.s, z1.s
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; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
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; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
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; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: splice z3.s, p1, z3.s, z2.s
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|
; CHECK-NEXT: stp q0, q3, [x1]
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|
; CHECK-NEXT: ret
|
|
%op1 = load <8 x double>, <8 x double>* %a
|
|
%res = fptosi <8 x double> %op1 to <8 x i32>
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|
store <8 x i32> %res, <8 x i32>* %b
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|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS D -> D
|
|
;
|
|
|
|
define <1 x i64> @fcvtzs_v1f64_v1i64(<1 x double> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v1f64_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzs x8, d0
|
|
; CHECK-NEXT: fmov d0, x8
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <1 x double> %op1 to <1 x i64>
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
define <2 x i64> @fcvtzs_v2f64_v2i64(<2 x double> %op1) #0 {
|
|
; CHECK-LABEL: fcvtzs_v2f64_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = fptosi <2 x double> %op1 to <2 x i64>
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @fcvtzs_v4f64_v4i64(<4 x double>* %a, <4 x i64>* %b) #0 {
|
|
; CHECK-LABEL: fcvtzs_v4f64_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <4 x double>, <4 x double>* %a
|
|
%res = fptosi <4 x double> %op1 to <4 x i64>
|
|
store <4 x i64> %res, <4 x i64>* %b
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { "target-features"="+sve" }
|