forked from OSchip/llvm-project
287 lines
9.9 KiB
LLVM
287 lines
9.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v2f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: adrp x9, .LCPI0_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI0_0]
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; CHECK-NEXT: strh w8, [sp, #14]
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; CHECK-NEXT: strh w8, [sp, #12]
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; CHECK-NEXT: strh w8, [sp, #10]
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; CHECK-NEXT: strh w8, [sp, #8]
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; CHECK-NEXT: ldr d2, [sp, #8]
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <2 x half> %op1, <2 x half> %op2
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ret <2 x half> %sel
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}
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define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: adrp x9, .LCPI1_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI1_0]
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; CHECK-NEXT: strh w8, [sp, #14]
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; CHECK-NEXT: strh w8, [sp, #12]
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; CHECK-NEXT: strh w8, [sp, #10]
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; CHECK-NEXT: strh w8, [sp, #8]
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; CHECK-NEXT: ldr d2, [sp, #8]
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <4 x half> %op1, <4 x half> %op2
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ret <4 x half> %sel
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}
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define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: adrp x9, .LCPI2_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI2_0]
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; CHECK-NEXT: strh w8, [sp, #14]
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; CHECK-NEXT: strh w8, [sp, #12]
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; CHECK-NEXT: strh w8, [sp, #10]
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; CHECK-NEXT: strh w8, [sp, #8]
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; CHECK-NEXT: strh w8, [sp, #6]
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; CHECK-NEXT: strh w8, [sp, #4]
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; CHECK-NEXT: strh w8, [sp, #2]
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; CHECK-NEXT: strh w8, [sp]
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; CHECK-NEXT: ldr q2, [sp]
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <8 x half> %op1, <8 x half> %op2
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ret <8 x half> %sel
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}
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define void @select_v16f16(ptr %a, ptr %b, i1 %mask) #0 {
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; CHECK-LABEL: select_v16f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w2, #0x1
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; CHECK-NEXT: adrp x9, .LCPI3_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x0, #16]
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; CHECK-NEXT: ldr q2, [x1]
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; CHECK-NEXT: ldr q3, [x1, #16]
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; CHECK-NEXT: strh w8, [sp, #14]
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; CHECK-NEXT: strh w8, [sp, #12]
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; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI3_0]
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; CHECK-NEXT: strh w8, [sp, #10]
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; CHECK-NEXT: strh w8, [sp, #8]
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; CHECK-NEXT: strh w8, [sp, #6]
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; CHECK-NEXT: strh w8, [sp, #4]
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; CHECK-NEXT: strh w8, [sp, #2]
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; CHECK-NEXT: strh w8, [sp]
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; CHECK-NEXT: ldr q4, [sp]
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; CHECK-NEXT: eor z5.d, z4.d, z5.d
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; CHECK-NEXT: and z1.d, z1.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z4.d
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; CHECK-NEXT: and z2.d, z2.d, z5.d
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; CHECK-NEXT: and z3.d, z3.d, z5.d
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; CHECK-NEXT: orr z0.d, z0.d, z2.d
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; CHECK-NEXT: orr z1.d, z1.d, z3.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%op1 = load volatile <16 x half>, ptr %a
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%op2 = load volatile <16 x half>, ptr %b
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%sel = select i1 %mask, <16 x half> %op1, <16 x half> %op2
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store <16 x half> %sel, ptr %a
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ret void
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}
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define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: adrp x9, .LCPI4_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI4_0]
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; CHECK-NEXT: stp w8, w8, [sp, #8]
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; CHECK-NEXT: ldr d2, [sp, #8]
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <2 x float> %op1, <2 x float> %op2
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ret <2 x float> %sel
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}
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define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: adrp x9, .LCPI5_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI5_0]
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; CHECK-NEXT: stp w8, w8, [sp, #8]
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; CHECK-NEXT: stp w8, w8, [sp]
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; CHECK-NEXT: ldr q2, [sp]
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <4 x float> %op1, <4 x float> %op2
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ret <4 x float> %sel
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}
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define void @select_v8f32(ptr %a, ptr %b, i1 %mask) #0 {
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; CHECK-LABEL: select_v8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: tst w2, #0x1
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; CHECK-NEXT: adrp x9, .LCPI6_0
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x0, #16]
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; CHECK-NEXT: ldr q2, [x1]
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; CHECK-NEXT: ldr q3, [x1, #16]
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; CHECK-NEXT: stp w8, w8, [sp, #8]
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; CHECK-NEXT: stp w8, w8, [sp]
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; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI6_0]
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; CHECK-NEXT: ldr q4, [sp]
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; CHECK-NEXT: eor z5.d, z4.d, z5.d
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; CHECK-NEXT: and z1.d, z1.d, z4.d
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; CHECK-NEXT: and z0.d, z0.d, z4.d
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; CHECK-NEXT: and z2.d, z2.d, z5.d
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; CHECK-NEXT: and z3.d, z3.d, z5.d
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; CHECK-NEXT: orr z0.d, z0.d, z2.d
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; CHECK-NEXT: orr z1.d, z1.d, z3.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%op1 = load volatile <8 x float>, ptr %a
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%op2 = load volatile <8 x float>, ptr %b
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%sel = select i1 %mask, <8 x float> %op1, <8 x float> %op2
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store <8 x float> %sel, ptr %a
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ret void
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}
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define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v1f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: mov x9, #-1
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; CHECK-NEXT: csetm x8, ne
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: fmov d3, x9
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; CHECK-NEXT: fmov d2, x8
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <1 x double> %op1, <1 x double> %op2
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ret <1 x double> %sel
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}
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define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, i1 %mask) #0 {
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; CHECK-LABEL: select_v2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: adrp x9, .LCPI8_0
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; CHECK-NEXT: csetm x8, ne
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; CHECK-NEXT: stp x8, x8, [sp, #-16]!
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: ldr q2, [sp]
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; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI8_0]
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; CHECK-NEXT: and z0.d, z0.d, z2.d
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; CHECK-NEXT: eor z3.d, z2.d, z3.d
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; CHECK-NEXT: and z1.d, z1.d, z3.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <2 x double> %op1, <2 x double> %op2
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ret <2 x double> %sel
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}
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define void @select_v4f64(ptr %a, ptr %b, i1 %mask) #0 {
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; CHECK-LABEL: select_v4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w2, #0x1
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: csetm x8, ne
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; CHECK-NEXT: ldr q1, [x0, #16]
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; CHECK-NEXT: ldr q2, [x1]
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; CHECK-NEXT: adrp x9, .LCPI9_0
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; CHECK-NEXT: ldr q3, [x1, #16]
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; CHECK-NEXT: stp x8, x8, [sp, #-16]!
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI9_0]
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; CHECK-NEXT: ldr q5, [sp]
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; CHECK-NEXT: eor z4.d, z5.d, z4.d
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; CHECK-NEXT: and z1.d, z1.d, z5.d
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; CHECK-NEXT: and z0.d, z0.d, z5.d
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; CHECK-NEXT: and z2.d, z2.d, z4.d
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; CHECK-NEXT: and z3.d, z3.d, z4.d
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; CHECK-NEXT: orr z0.d, z0.d, z2.d
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; CHECK-NEXT: orr z1.d, z1.d, z3.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%op1 = load volatile <4 x double>, ptr %a
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%op2 = load volatile <4 x double>, ptr %b
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%sel = select i1 %mask, <4 x double> %op1, <4 x double> %op2
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store <4 x double> %sel, ptr %a
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ret void
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}
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attributes #0 = { "target-features"="+sve" }
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