forked from OSchip/llvm-project
320 lines
11 KiB
LLVM
320 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; i1
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define <4 x i1> @extract_subvector_v8i1(<8 x i1> %op) #0 {
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; CHECK-LABEL: extract_subvector_v8i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: mov z1.b, z0.b[7]
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; CHECK-NEXT: mov z2.b, z0.b[6]
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; CHECK-NEXT: fmov w8, s1
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; CHECK-NEXT: mov z1.b, z0.b[5]
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; CHECK-NEXT: mov z0.b, z0.b[4]
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; CHECK-NEXT: fmov w9, s2
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; CHECK-NEXT: fmov w10, s1
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; CHECK-NEXT: fmov w11, s0
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; CHECK-NEXT: strh w8, [sp, #14]
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; CHECK-NEXT: strh w9, [sp, #12]
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; CHECK-NEXT: strh w10, [sp, #10]
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; CHECK-NEXT: strh w11, [sp, #8]
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; CHECK-NEXT: ldr d0, [sp, #8]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%ret = call <4 x i1> @llvm.vector.extract.v4i1.v8i1(<8 x i1> %op, i64 4)
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ret <4 x i1> %ret
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}
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; i8
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define <4 x i8> @extract_subvector_v8i8(<8 x i8> %op) #0 {
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; CHECK-LABEL: extract_subvector_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: mov z1.b, z0.b[7]
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; CHECK-NEXT: mov z2.b, z0.b[6]
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; CHECK-NEXT: fmov w8, s1
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; CHECK-NEXT: mov z1.b, z0.b[5]
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; CHECK-NEXT: mov z0.b, z0.b[4]
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; CHECK-NEXT: fmov w9, s2
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; CHECK-NEXT: fmov w10, s1
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; CHECK-NEXT: fmov w11, s0
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; CHECK-NEXT: strh w8, [sp, #14]
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; CHECK-NEXT: strh w9, [sp, #12]
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; CHECK-NEXT: strh w10, [sp, #10]
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; CHECK-NEXT: strh w11, [sp, #8]
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; CHECK-NEXT: ldr d0, [sp, #8]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%ret = call <4 x i8> @llvm.vector.extract.v4i8.v8i8(<8 x i8> %op, i64 4)
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ret <4 x i8> %ret
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}
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define <8 x i8> @extract_subvector_v16i8(<16 x i8> %op) #0 {
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; CHECK-LABEL: extract_subvector_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%ret = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %op, i64 8)
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ret <8 x i8> %ret
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}
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define void @extract_subvector_v32i8(<32 x i8>* %a, <16 x i8>* %b) #0 {
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; CHECK-LABEL: extract_subvector_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0, #16]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%op = load <32 x i8>, <32 x i8>* %a
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%ret = call <16 x i8> @llvm.vector.extract.v16i8.v32i8(<32 x i8> %op, i64 16)
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store <16 x i8> %ret, <16 x i8>* %b
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ret void
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}
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; i16
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define <2 x i16> @extract_subvector_v4i16(<4 x i16> %op) #0 {
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; CHECK-LABEL: extract_subvector_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: uunpklo z0.s, z0.h
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; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%ret = call <2 x i16> @llvm.vector.extract.v2i16.v4i16(<4 x i16> %op, i64 2)
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ret <2 x i16> %ret
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}
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define <4 x i16> @extract_subvector_v8i16(<8 x i16> %op) #0 {
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; CHECK-LABEL: extract_subvector_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%ret = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %op, i64 4)
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ret <4 x i16> %ret
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}
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define void @extract_subvector_v16i16(<16 x i16>* %a, <8 x i16>* %b) #0 {
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; CHECK-LABEL: extract_subvector_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0, #16]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%op = load <16 x i16>, <16 x i16>* %a
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%ret = call <8 x i16> @llvm.vector.extract.v8i16.v16i16(<16 x i16> %op, i64 8)
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store <8 x i16> %ret, <8 x i16>* %b
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ret void
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}
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; i32
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define <1 x i32> @extract_subvector_v2i32(<2 x i32> %op) #0 {
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; CHECK-LABEL: extract_subvector_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: mov z0.s, z0.s[1]
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%ret = call <1 x i32> @llvm.vector.extract.v1i32.v2i32(<2 x i32> %op, i64 1)
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ret <1 x i32> %ret
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}
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define <2 x i32> @extract_subvector_v4i32(<4 x i32> %op) #0 {
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; CHECK-LABEL: extract_subvector_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%ret = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %op, i64 2)
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ret <2 x i32> %ret
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}
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define void @extract_subvector_v8i32(<8 x i32>* %a, <4 x i32>* %b) #0 {
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; CHECK-LABEL: extract_subvector_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0, #16]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%op = load <8 x i32>, <8 x i32>* %a
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%ret = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %op, i64 4)
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store <4 x i32> %ret, <4 x i32>* %b
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ret void
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}
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; i64
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define <1 x i64> @extract_subvector_v2i64(<2 x i64> %op) #0 {
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; CHECK-LABEL: extract_subvector_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%ret = call <1 x i64> @llvm.vector.extract.v1i64.v2i64(<2 x i64> %op, i64 1)
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ret <1 x i64> %ret
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}
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define void @extract_subvector_v4i64(<4 x i64>* %a, <2 x i64>* %b) #0 {
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; CHECK-LABEL: extract_subvector_v4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0, #16]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%op = load <4 x i64>, <4 x i64>* %a
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%ret = call <2 x i64> @llvm.vector.extract.v2i64.v4i64(<4 x i64> %op, i64 2)
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store <2 x i64> %ret, <2 x i64>* %b
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ret void
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}
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; f16
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define <2 x half> @extract_subvector_v4f16(<4 x half> %op) #0 {
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; CHECK-LABEL: extract_subvector_v4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: mov z1.h, z0.h[3]
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; CHECK-NEXT: mov z0.h, z0.h[2]
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; CHECK-NEXT: str h1, [sp, #10]
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; CHECK-NEXT: str h0, [sp, #8]
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; CHECK-NEXT: ldr d0, [sp, #8]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%ret = call <2 x half> @llvm.vector.extract.v2f16.v4f16(<4 x half> %op, i64 2)
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ret <2 x half> %ret
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}
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define <4 x half> @extract_subvector_v8f16(<8 x half> %op) #0 {
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; CHECK-LABEL: extract_subvector_v8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%ret = call <4 x half> @llvm.vector.extract.v4f16.v8f16(<8 x half> %op, i64 4)
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ret <4 x half> %ret
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}
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define void @extract_subvector_v16f16(<16 x half>* %a, <8 x half>* %b) #0 {
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; CHECK-LABEL: extract_subvector_v16f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0, #16]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%op = load <16 x half>, <16 x half>* %a
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%ret = call <8 x half> @llvm.vector.extract.v8f16.v16f16(<16 x half> %op, i64 8)
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store <8 x half> %ret, <8 x half>* %b
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ret void
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}
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; f32
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define <1 x float> @extract_subvector_v2f32(<2 x float> %op) #0 {
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; CHECK-LABEL: extract_subvector_v2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: mov z0.s, z0.s[1]
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%ret = call <1 x float> @llvm.vector.extract.v1f32.v2f32(<2 x float> %op, i64 1)
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ret <1 x float> %ret
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}
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define <2 x float> @extract_subvector_v4f32(<4 x float> %op) #0 {
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; CHECK-LABEL: extract_subvector_v4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%ret = call <2 x float> @llvm.vector.extract.v2f32.v4f32(<4 x float> %op, i64 2)
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ret <2 x float> %ret
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}
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define void @extract_subvector_v8f32(<8 x float>* %a, <4 x float>* %b) #0 {
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; CHECK-LABEL: extract_subvector_v8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0, #16]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%op = load <8 x float>, <8 x float>* %a
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%ret = call <4 x float> @llvm.vector.extract.v4f32.v8f32(<8 x float> %op, i64 4)
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store <4 x float> %ret, <4 x float>* %b
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ret void
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}
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; f64
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define <1 x double> @extract_subvector_v2f64(<2 x double> %op) #0 {
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; CHECK-LABEL: extract_subvector_v2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%ret = call <1 x double> @llvm.vector.extract.v1f64.v2f64(<2 x double> %op, i64 1)
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ret <1 x double> %ret
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}
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define void @extract_subvector_v4f64(<4 x double>* %a, <2 x double>* %b) #0 {
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; CHECK-LABEL: extract_subvector_v4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0, #16]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%op = load <4 x double>, <4 x double>* %a
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%ret = call <2 x double> @llvm.vector.extract.v2f64.v4f64(<4 x double> %op, i64 2)
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store <2 x double> %ret, <2 x double>* %b
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ret void
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}
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declare <4 x i1> @llvm.vector.extract.v4i1.v8i1(<8 x i1>, i64)
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declare <4 x i8> @llvm.vector.extract.v4i8.v8i8(<8 x i8>, i64)
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declare <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8>, i64)
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declare <16 x i8> @llvm.vector.extract.v16i8.v32i8(<32 x i8>, i64)
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declare <32 x i8> @llvm.vector.extract.v32i8.v64i8(<64 x i8>, i64)
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declare <2 x i16> @llvm.vector.extract.v2i16.v4i16(<4 x i16>, i64)
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declare <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16>, i64)
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declare <8 x i16> @llvm.vector.extract.v8i16.v16i16(<16 x i16>, i64)
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declare <16 x i16> @llvm.vector.extract.v16i16.v32i16(<32 x i16>, i64)
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declare <1 x i32> @llvm.vector.extract.v1i32.v2i32(<2 x i32>, i64)
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declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32>, i64)
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declare <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32>, i64)
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declare <8 x i32> @llvm.vector.extract.v8i32.v16i32(<16 x i32>, i64)
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declare <1 x i64> @llvm.vector.extract.v1i64.v2i64(<2 x i64>, i64)
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declare <2 x i64> @llvm.vector.extract.v2i64.v4i64(<4 x i64>, i64)
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declare <4 x i64> @llvm.vector.extract.v4i64.v8i64(<8 x i64>, i64)
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declare <2 x half> @llvm.vector.extract.v2f16.v4f16(<4 x half>, i64)
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declare <4 x half> @llvm.vector.extract.v4f16.v8f16(<8 x half>, i64)
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declare <8 x half> @llvm.vector.extract.v8f16.v16f16(<16 x half>, i64)
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declare <16 x half> @llvm.vector.extract.v16f16.v32f16(<32 x half>, i64)
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declare <1 x float> @llvm.vector.extract.v1f32.v2f32(<2 x float>, i64)
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declare <2 x float> @llvm.vector.extract.v2f32.v4f32(<4 x float>, i64)
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declare <4 x float> @llvm.vector.extract.v4f32.v8f32(<8 x float>, i64)
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declare <8 x float> @llvm.vector.extract.v8f32.v16f32(<16 x float>, i64)
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declare <1 x double> @llvm.vector.extract.v1f64.v2f64(<2 x double>, i64)
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declare <2 x double> @llvm.vector.extract.v2f64.v4f64(<4 x double>, i64)
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declare <4 x double> @llvm.vector.extract.v4f64.v8f64(<8 x double>, i64)
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attributes #0 = { "target-features"="+sve" }
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