forked from OSchip/llvm-project
209 lines
6.9 KiB
LLVM
209 lines
6.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define <8 x i16> @load_zext_v8i8i16(<8 x i8>* %ap) #0 {
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; CHECK-LABEL: load_zext_v8i8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp s1, s0, [x0]
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: uunpklo z2.h, z0.b
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; CHECK-NEXT: uunpklo z0.h, z1.b
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; CHECK-NEXT: splice z0.h, p0, z0.h, z2.h
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%a = load <8 x i8>, <8 x i8>* %ap
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%val = zext <8 x i8> %a to <8 x i16>
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ret <8 x i16> %val
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}
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define <4 x i32> @load_zext_v4i16i32(<4 x i16>* %ap) #0 {
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; CHECK-LABEL: load_zext_v4i16i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: uunpklo z0.s, z0.h
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%a = load <4 x i16>, <4 x i16>* %ap
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%val = zext <4 x i16> %a to <4 x i32>
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ret <4 x i32> %val
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}
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define <2 x i64> @load_zext_v2i32i64(<2 x i32>* %ap) #0 {
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; CHECK-LABEL: load_zext_v2i32i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: uunpklo z0.d, z0.s
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%a = load <2 x i32>, <2 x i32>* %ap
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%val = zext <2 x i32> %a to <2 x i64>
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ret <2 x i64> %val
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}
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define <2 x i256> @load_zext_v2i64i256(<2 x i64>* %ap) #0 {
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; CHECK-LABEL: load_zext_v2i64i256:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI3_0
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: mov x1, xzr
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; CHECK-NEXT: mov x5, xzr
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
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; CHECK-NEXT: mov z2.d, z0.d[1]
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: fmov x4, d2
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; CHECK-NEXT: mov z0.d, z1.d[1]
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; CHECK-NEXT: fmov x2, d1
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; CHECK-NEXT: fmov x3, d0
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; CHECK-NEXT: mov x6, x2
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; CHECK-NEXT: mov x7, x3
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; CHECK-NEXT: ret
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%a = load <2 x i64>, <2 x i64>* %ap
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%val = zext <2 x i64> %a to <2 x i256>
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ret <2 x i256> %val
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}
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define <16 x i32> @load_sext_v16i8i32(<16 x i8>* %ap) #0 {
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; CHECK-LABEL: load_sext_v16i8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q1, [x0]
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; CHECK-NEXT: sunpklo z3.h, z1.b
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; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
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; CHECK-NEXT: sunpklo z4.h, z1.b
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; CHECK-NEXT: sunpklo z0.s, z3.h
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; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
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; CHECK-NEXT: sunpklo z2.s, z4.h
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; CHECK-NEXT: ext z4.b, z4.b, z4.b, #8
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; CHECK-NEXT: sunpklo z1.s, z3.h
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; CHECK-NEXT: sunpklo z3.s, z4.h
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
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; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
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; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
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; CHECK-NEXT: ret
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%a = load <16 x i8>, <16 x i8>* %ap
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%val = sext <16 x i8> %a to <16 x i32>
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ret <16 x i32> %val
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}
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define <8 x i32> @load_sext_v8i16i32(<8 x i16>* %ap) #0 {
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; CHECK-LABEL: load_sext_v8i16i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q1, [x0]
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; CHECK-NEXT: sunpklo z0.s, z1.h
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; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
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; CHECK-NEXT: sunpklo z1.s, z1.h
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
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; CHECK-NEXT: ret
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%a = load <8 x i16>, <8 x i16>* %ap
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%val = sext <8 x i16> %a to <8 x i32>
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ret <8 x i32> %val
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}
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define <4 x i256> @load_sext_v4i32i256(<4 x i32>* %ap) #0 {
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; CHECK-LABEL: load_sext_v4i32i256:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: sunpklo z1.d, z0.s
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; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
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; CHECK-NEXT: fmov x9, d1
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; CHECK-NEXT: sunpklo z0.d, z0.s
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; CHECK-NEXT: fmov x11, d0
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; CHECK-NEXT: mov z0.d, z0.d[1]
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; CHECK-NEXT: asr x10, x9, #63
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; CHECK-NEXT: asr x12, x11, #63
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; CHECK-NEXT: stp x9, x10, [x8]
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: mov z0.d, z1.d[1]
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; CHECK-NEXT: stp x11, x12, [x8, #64]
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; CHECK-NEXT: fmov x11, d0
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; CHECK-NEXT: stp x10, x10, [x8, #16]
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; CHECK-NEXT: stp x12, x12, [x8, #80]
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; CHECK-NEXT: asr x10, x9, #63
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; CHECK-NEXT: asr x12, x11, #63
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; CHECK-NEXT: stp x10, x10, [x8, #112]
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; CHECK-NEXT: stp x9, x10, [x8, #96]
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; CHECK-NEXT: stp x12, x12, [x8, #48]
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; CHECK-NEXT: stp x11, x12, [x8, #32]
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; CHECK-NEXT: ret
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%a = load <4 x i32>, <4 x i32>* %ap
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%val = sext <4 x i32> %a to <4 x i256>
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ret <4 x i256> %val
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}
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define <2 x i256> @load_sext_v2i64i256(<2 x i64>* %ap) #0 {
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; CHECK-LABEL: load_sext_v2i64i256:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #64
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: mov z0.d, z0.d[1]
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; CHECK-NEXT: asr x9, x8, #63
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; CHECK-NEXT: stp x8, x9, [sp, #16]
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: stp x9, x9, [sp]
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; CHECK-NEXT: ldp q1, q0, [sp]
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; CHECK-NEXT: asr x10, x8, #63
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; CHECK-NEXT: stp x8, x10, [sp, #48]
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; CHECK-NEXT: fmov x2, d1
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; CHECK-NEXT: stp x10, x10, [sp, #32]
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; CHECK-NEXT: ldp q3, q2, [sp, #32]
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; CHECK-NEXT: mov z4.d, z0.d[1]
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: mov z0.d, z1.d[1]
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; CHECK-NEXT: fmov x1, d4
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; CHECK-NEXT: fmov x3, d0
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; CHECK-NEXT: fmov x6, d3
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; CHECK-NEXT: mov z1.d, z2.d[1]
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; CHECK-NEXT: fmov x4, d2
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; CHECK-NEXT: mov z2.d, z3.d[1]
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; CHECK-NEXT: fmov x5, d1
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; CHECK-NEXT: fmov x7, d2
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; CHECK-NEXT: add sp, sp, #64
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; CHECK-NEXT: ret
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%a = load <2 x i64>, <2 x i64>* %ap
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%val = sext <2 x i64> %a to <2 x i256>
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ret <2 x i256> %val
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}
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define <16 x i64> @load_zext_v16i16i64(<16 x i16>* %ap) #0 {
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; CHECK-LABEL: load_zext_v16i16i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q2, [x0]
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; CHECK-NEXT: uunpklo z3.s, z1.h
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; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
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; CHECK-NEXT: uunpklo z7.s, z1.h
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; CHECK-NEXT: uunpklo z0.d, z3.s
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; CHECK-NEXT: uunpklo z5.s, z2.h
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; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
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; CHECK-NEXT: uunpklo z16.s, z2.h
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; CHECK-NEXT: uunpklo z4.d, z5.s
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; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
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; CHECK-NEXT: ext z5.b, z5.b, z5.b, #8
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; CHECK-NEXT: uunpklo z2.d, z7.s
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; CHECK-NEXT: uunpklo z6.d, z16.s
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; CHECK-NEXT: ext z7.b, z7.b, z7.b, #8
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; CHECK-NEXT: ext z16.b, z16.b, z16.b, #8
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; CHECK-NEXT: uunpklo z1.d, z3.s
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; CHECK-NEXT: uunpklo z5.d, z5.s
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; CHECK-NEXT: uunpklo z3.d, z7.s
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; CHECK-NEXT: uunpklo z7.d, z16.s
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
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; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
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; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
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; CHECK-NEXT: // kill: def $q4 killed $q4 killed $z4
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; CHECK-NEXT: // kill: def $q5 killed $q5 killed $z5
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; CHECK-NEXT: // kill: def $q6 killed $q6 killed $z6
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; CHECK-NEXT: // kill: def $q7 killed $q7 killed $z7
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; CHECK-NEXT: ret
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%a = load <16 x i16>, <16 x i16>* %ap
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%val = zext <16 x i16> %a to <16 x i64>
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ret <16 x i64> %val
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}
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attributes #0 = { "target-features"="+sve" }
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