forked from OSchip/llvm-project
362 lines
12 KiB
LLVM
362 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
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; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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target triple = "aarch64-unknown-linux-gnu"
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;
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; insertelement
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;
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; Don't use SVE for 64-bit vectors.
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define <4 x half> @insertelement_v4f16(<4 x half> %op1) vscale_range(2,0) #0 {
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; CHECK-LABEL: insertelement_v4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov h1, #5.00000000
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: mov v0.h[3], v1.h[0]
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%r = insertelement <4 x half> %op1, half 5.0, i64 3
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ret <4 x half> %r
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}
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; Don't use SVE for 128-bit vectors.
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define <8 x half> @insertelement_v8f16(<8 x half> %op1) vscale_range(2,0) #0 {
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; CHECK-LABEL: insertelement_v8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov h1, #5.00000000
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; CHECK-NEXT: mov v0.h[7], v1.h[0]
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; CHECK-NEXT: ret
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%r = insertelement <8 x half> %op1, half 5.0, i64 7
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ret <8 x half> %r
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}
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define <16 x half> @insertelement_v16f16(ptr %a) vscale_range(2,0) #0 {
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; CHECK-LABEL: insertelement_v16f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w9, #15
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; CHECK-NEXT: ptrue p0.h, vl16
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: fmov h2, #5.00000000
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; CHECK-NEXT: index z3.h, #0, #1
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: mov z1.h, w9
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; CHECK-NEXT: cmpeq p1.h, p1/z, z3.h, z1.h
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; CHECK-NEXT: mov z0.h, p1/m, h2
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; CHECK-NEXT: st1h { z0.h }, p0, [x8]
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; CHECK-NEXT: ret
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%op1 = load <16 x half>, ptr %a
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%r = insertelement <16 x half> %op1, half 5.0, i64 15
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ret <16 x half> %r
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}
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define <32 x half> @insertelement_v32f16(ptr %a) #0 {
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; VBITS_GE_256-LABEL: insertelement_v32f16:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: mov x9, #16
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; VBITS_GE_256-NEXT: mov w10, #15
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; VBITS_GE_256-NEXT: ptrue p0.h, vl16
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; VBITS_GE_256-NEXT: fmov h3, #5.00000000
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; VBITS_GE_256-NEXT: index z4.h, #0, #1
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; VBITS_GE_256-NEXT: ptrue p1.h
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; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x9, lsl #1]
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; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]
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; VBITS_GE_256-NEXT: mov z2.h, w10
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; VBITS_GE_256-NEXT: cmpeq p1.h, p1/z, z4.h, z2.h
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; VBITS_GE_256-NEXT: mov z0.h, p1/m, h3
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; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x8, x9, lsl #1]
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; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x8]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: insertelement_v32f16:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: mov w9, #31
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; VBITS_GE_512-NEXT: ptrue p0.h, vl32
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; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
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; VBITS_GE_512-NEXT: fmov h2, #5.00000000
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; VBITS_GE_512-NEXT: index z3.h, #0, #1
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; VBITS_GE_512-NEXT: ptrue p1.h
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; VBITS_GE_512-NEXT: mov z1.h, w9
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; VBITS_GE_512-NEXT: cmpeq p1.h, p1/z, z3.h, z1.h
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; VBITS_GE_512-NEXT: mov z0.h, p1/m, h2
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; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x8]
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; VBITS_GE_512-NEXT: ret
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%op1 = load <32 x half>, ptr %a
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%r = insertelement <32 x half> %op1, half 5.0, i64 31
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ret <32 x half> %r
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}
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define <64 x half> @insertelement_v64f16(ptr %a) vscale_range(8,0) #0 {
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; CHECK-LABEL: insertelement_v64f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w9, #63
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; CHECK-NEXT: ptrue p0.h, vl64
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: fmov h2, #5.00000000
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; CHECK-NEXT: index z3.h, #0, #1
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: mov z1.h, w9
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; CHECK-NEXT: cmpeq p1.h, p1/z, z3.h, z1.h
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; CHECK-NEXT: mov z0.h, p1/m, h2
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; CHECK-NEXT: st1h { z0.h }, p0, [x8]
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; CHECK-NEXT: ret
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%op1 = load <64 x half>, ptr %a
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%r = insertelement <64 x half> %op1, half 5.0, i64 63
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ret <64 x half> %r
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}
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define <128 x half> @insertelement_v128f16(ptr %a) vscale_range(16,0) #0 {
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; CHECK-LABEL: insertelement_v128f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w9, #127
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; CHECK-NEXT: ptrue p0.h, vl128
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: fmov h2, #5.00000000
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; CHECK-NEXT: index z3.h, #0, #1
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: mov z1.h, w9
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; CHECK-NEXT: cmpeq p1.h, p1/z, z3.h, z1.h
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; CHECK-NEXT: mov z0.h, p1/m, h2
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; CHECK-NEXT: st1h { z0.h }, p0, [x8]
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; CHECK-NEXT: ret
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%op1 = load <128 x half>, ptr %a
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%r = insertelement <128 x half> %op1, half 5.0, i64 127
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ret <128 x half> %r
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}
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; Don't use SVE for 64-bit vectors.
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define <2 x float> @insertelement_v2f32(<2 x float> %op1) vscale_range(2,0) #0 {
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; CHECK-LABEL: insertelement_v2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s1, #5.00000000
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: mov v0.s[1], v1.s[0]
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%r = insertelement <2 x float> %op1, float 5.0, i64 1
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ret <2 x float> %r
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}
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; Don't use SVE for 128-bit vectors.
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define <4 x float> @insertelement_v4f32(<4 x float> %op1) vscale_range(2,0) #0 {
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; CHECK-LABEL: insertelement_v4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s1, #5.00000000
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; CHECK-NEXT: mov v0.s[3], v1.s[0]
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; CHECK-NEXT: ret
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%r = insertelement <4 x float> %op1, float 5.0, i64 3
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ret <4 x float> %r
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}
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define <8 x float> @insertelement_v8f32(ptr %a) vscale_range(2,0) #0 {
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; CHECK-LABEL: insertelement_v8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w9, #7
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; CHECK-NEXT: ptrue p0.s, vl8
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: fmov s2, #5.00000000
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; CHECK-NEXT: index z3.s, #0, #1
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: mov z1.s, w9
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; CHECK-NEXT: cmpeq p1.s, p1/z, z3.s, z1.s
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; CHECK-NEXT: mov z0.s, p1/m, s2
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; CHECK-NEXT: st1w { z0.s }, p0, [x8]
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; CHECK-NEXT: ret
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%op1 = load <8 x float>, ptr %a
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%r = insertelement <8 x float> %op1, float 5.0, i64 7
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ret <8 x float> %r
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}
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define <16 x float> @insertelement_v16f32(ptr %a) #0 {
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; VBITS_GE_256-LABEL: insertelement_v16f32:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: mov x9, #8
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; VBITS_GE_256-NEXT: mov w10, #7
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; VBITS_GE_256-NEXT: ptrue p0.s, vl8
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; VBITS_GE_256-NEXT: fmov s3, #5.00000000
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; VBITS_GE_256-NEXT: index z4.s, #0, #1
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; VBITS_GE_256-NEXT: ptrue p1.s
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; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x9, lsl #2]
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; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]
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; VBITS_GE_256-NEXT: mov z2.s, w10
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; VBITS_GE_256-NEXT: cmpeq p1.s, p1/z, z4.s, z2.s
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; VBITS_GE_256-NEXT: mov z0.s, p1/m, s3
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; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x8, x9, lsl #2]
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; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x8]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: insertelement_v16f32:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: mov w9, #15
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; VBITS_GE_512-NEXT: ptrue p0.s, vl16
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; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_512-NEXT: fmov s2, #5.00000000
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; VBITS_GE_512-NEXT: index z3.s, #0, #1
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; VBITS_GE_512-NEXT: ptrue p1.s
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; VBITS_GE_512-NEXT: mov z1.s, w9
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; VBITS_GE_512-NEXT: cmpeq p1.s, p1/z, z3.s, z1.s
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; VBITS_GE_512-NEXT: mov z0.s, p1/m, s2
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; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x8]
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; VBITS_GE_512-NEXT: ret
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%op1 = load <16 x float>, ptr %a
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%r = insertelement <16 x float> %op1, float 5.0, i64 15
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ret <16 x float> %r
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}
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define <32 x float> @insertelement_v32f32(ptr %a) vscale_range(8,0) #0 {
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; CHECK-LABEL: insertelement_v32f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w9, #31
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; CHECK-NEXT: ptrue p0.s, vl32
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: fmov s2, #5.00000000
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; CHECK-NEXT: index z3.s, #0, #1
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: mov z1.s, w9
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; CHECK-NEXT: cmpeq p1.s, p1/z, z3.s, z1.s
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; CHECK-NEXT: mov z0.s, p1/m, s2
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; CHECK-NEXT: st1w { z0.s }, p0, [x8]
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; CHECK-NEXT: ret
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%op1 = load <32 x float>, ptr %a
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%r = insertelement <32 x float> %op1, float 5.0, i64 31
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ret <32 x float> %r
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}
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define <64 x float> @insertelement_v64f32(ptr %a) vscale_range(16,0) #0 {
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; CHECK-LABEL: insertelement_v64f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w9, #63
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; CHECK-NEXT: ptrue p0.s, vl64
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: fmov s2, #5.00000000
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; CHECK-NEXT: index z3.s, #0, #1
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: mov z1.s, w9
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; CHECK-NEXT: cmpeq p1.s, p1/z, z3.s, z1.s
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; CHECK-NEXT: mov z0.s, p1/m, s2
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; CHECK-NEXT: st1w { z0.s }, p0, [x8]
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; CHECK-NEXT: ret
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%op1 = load <64 x float>, ptr %a
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%r = insertelement <64 x float> %op1, float 5.0, i64 63
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ret <64 x float> %r
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}
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; Don't use SVE for 64-bit vectors.
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define <1 x double> @insertelement_v1f64(<1 x double> %op1) vscale_range(2,0) #0 {
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; CHECK-LABEL: insertelement_v1f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4617315517961601024
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; CHECK-NEXT: fmov d0, x8
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; CHECK-NEXT: ret
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%r = insertelement <1 x double> %op1, double 5.0, i64 0
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ret <1 x double> %r
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}
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; Don't use SVE for 128-bit vectors.
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define <2 x double> @insertelement_v2f64(<2 x double> %op1) vscale_range(2,0) #0 {
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; CHECK-LABEL: insertelement_v2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov d1, #5.00000000
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; CHECK-NEXT: mov v0.d[1], v1.d[0]
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; CHECK-NEXT: ret
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%r = insertelement <2 x double> %op1, double 5.0, i64 1
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ret <2 x double> %r
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}
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define <4 x double> @insertelement_v4f64(ptr %a) vscale_range(2,0) #0 {
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; CHECK-LABEL: insertelement_v4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w9, #3
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; CHECK-NEXT: ptrue p0.d, vl4
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: fmov d2, #5.00000000
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; CHECK-NEXT: index z3.d, #0, #1
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: mov z1.d, x9
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; CHECK-NEXT: cmpeq p1.d, p1/z, z3.d, z1.d
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; CHECK-NEXT: mov z0.d, p1/m, d2
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; CHECK-NEXT: st1d { z0.d }, p0, [x8]
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; CHECK-NEXT: ret
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%op1 = load <4 x double>, ptr %a
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%r = insertelement <4 x double> %op1, double 5.0, i64 3
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ret <4 x double> %r
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}
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define <8 x double> @insertelement_v8f64(ptr %a) #0 {
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; VBITS_GE_256-LABEL: insertelement_v8f64:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: mov x9, #4
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; VBITS_GE_256-NEXT: mov w10, #3
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; VBITS_GE_256-NEXT: ptrue p0.d, vl4
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; VBITS_GE_256-NEXT: fmov d3, #5.00000000
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; VBITS_GE_256-NEXT: index z4.d, #0, #1
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; VBITS_GE_256-NEXT: ptrue p1.d
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; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x9, lsl #3]
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; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]
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; VBITS_GE_256-NEXT: mov z2.d, x10
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; VBITS_GE_256-NEXT: cmpeq p1.d, p1/z, z4.d, z2.d
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; VBITS_GE_256-NEXT: mov z0.d, p1/m, d3
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; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x8, x9, lsl #3]
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; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x8]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: insertelement_v8f64:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: mov w9, #7
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; VBITS_GE_512-NEXT: ptrue p0.d, vl8
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; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
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; VBITS_GE_512-NEXT: fmov d2, #5.00000000
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; VBITS_GE_512-NEXT: index z3.d, #0, #1
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; VBITS_GE_512-NEXT: ptrue p1.d
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; VBITS_GE_512-NEXT: mov z1.d, x9
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; VBITS_GE_512-NEXT: cmpeq p1.d, p1/z, z3.d, z1.d
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; VBITS_GE_512-NEXT: mov z0.d, p1/m, d2
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; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x8]
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; VBITS_GE_512-NEXT: ret
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%op1 = load <8 x double>, ptr %a
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%r = insertelement <8 x double> %op1, double 5.0, i64 7
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ret <8 x double> %r
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}
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define <16 x double> @insertelement_v16f64(ptr %a) vscale_range(8,0) #0 {
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; CHECK-LABEL: insertelement_v16f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w9, #15
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; CHECK-NEXT: ptrue p0.d, vl16
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: fmov d2, #5.00000000
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; CHECK-NEXT: index z3.d, #0, #1
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: mov z1.d, x9
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; CHECK-NEXT: cmpeq p1.d, p1/z, z3.d, z1.d
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; CHECK-NEXT: mov z0.d, p1/m, d2
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; CHECK-NEXT: st1d { z0.d }, p0, [x8]
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; CHECK-NEXT: ret
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%op1 = load <16 x double>, ptr %a
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%r = insertelement <16 x double> %op1, double 5.0, i64 15
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ret <16 x double> %r
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}
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define <32 x double> @insertelement_v32f64(ptr %a) vscale_range(16,0) #0 {
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; CHECK-LABEL: insertelement_v32f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w9, #31
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; CHECK-NEXT: ptrue p0.d, vl32
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: fmov d2, #5.00000000
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; CHECK-NEXT: index z3.d, #0, #1
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: mov z1.d, x9
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; CHECK-NEXT: cmpeq p1.d, p1/z, z3.d, z1.d
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; CHECK-NEXT: mov z0.d, p1/m, d2
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; CHECK-NEXT: st1d { z0.d }, p0, [x8]
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; CHECK-NEXT: ret
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%op1 = load <32 x double>, ptr %a
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%r = insertelement <32 x double> %op1, double 5.0, i64 31
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ret <32 x double> %r
|
|
}
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|
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attributes #0 = { "target-features"="+sve" }
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