forked from OSchip/llvm-project
386 lines
14 KiB
LLVM
386 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
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; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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target triple = "aarch64-unknown-linux-gnu"
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; Don't use SVE for 64-bit vectors.
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define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, i1 %mask) vscale_range(2,0) #0 {
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; CHECK-LABEL: select_v4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: dup v2.4h, w8
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; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <4 x half> %op1, <4 x half> %op2
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ret <4 x half> %sel
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}
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; Don't use SVE for 128-bit vectors.
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define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, i1 %mask) vscale_range(2,0) #0 {
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; CHECK-LABEL: select_v8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: dup v2.8h, w8
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; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <8 x half> %op1, <8 x half> %op2
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ret <8 x half> %sel
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}
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define void @select_v16f16(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 {
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; CHECK-LABEL: select_v16f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w2, #0x1
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; CHECK-NEXT: ptrue p0.h, vl16
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: mov z2.h, w8
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; CHECK-NEXT: and z2.h, z2.h, #0x1
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; CHECK-NEXT: cmpne p1.h, p1/z, z2.h, #0
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; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
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; CHECK-NEXT: st1h { z0.h }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load volatile <16 x half>, ptr %a
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%op2 = load volatile <16 x half>, ptr %b
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%sel = select i1 %mask, <16 x half> %op1, <16 x half> %op2
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store <16 x half> %sel, ptr %a
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ret void
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}
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define void @select_v32f16(ptr %a, ptr %b, i1 %mask) #0 {
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; VBITS_GE_256-LABEL: select_v32f16:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: mov x8, #16
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; VBITS_GE_256-NEXT: and w9, w2, #0x1
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; VBITS_GE_256-NEXT: ptrue p0.h, vl16
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; VBITS_GE_256-NEXT: ptrue p1.h
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; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
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; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]
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; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x1, x8, lsl #1]
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; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]
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; VBITS_GE_256-NEXT: mov z4.h, w9
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; VBITS_GE_256-NEXT: and z4.h, z4.h, #0x1
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; VBITS_GE_256-NEXT: cmpne p1.h, p1/z, z4.h, #0
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; VBITS_GE_256-NEXT: sel z1.h, p1, z1.h, z3.h
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; VBITS_GE_256-NEXT: sel z0.h, p1, z0.h, z2.h
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; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]
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; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x0]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: select_v32f16:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: and w8, w2, #0x1
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; VBITS_GE_512-NEXT: ptrue p0.h, vl32
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; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
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; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]
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; VBITS_GE_512-NEXT: ptrue p1.h
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; VBITS_GE_512-NEXT: mov z2.h, w8
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; VBITS_GE_512-NEXT: and z2.h, z2.h, #0x1
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; VBITS_GE_512-NEXT: cmpne p1.h, p1/z, z2.h, #0
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; VBITS_GE_512-NEXT: sel z0.h, p1, z0.h, z1.h
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; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x0]
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; VBITS_GE_512-NEXT: ret
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%op1 = load volatile <32 x half>, ptr %a
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%op2 = load volatile <32 x half>, ptr %b
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%sel = select i1 %mask, <32 x half> %op1, <32 x half> %op2
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store <32 x half> %sel, ptr %a
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ret void
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}
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define void @select_v64f16(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 {
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; CHECK-LABEL: select_v64f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w2, #0x1
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; CHECK-NEXT: ptrue p0.h, vl64
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: mov z2.h, w8
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; CHECK-NEXT: and z2.h, z2.h, #0x1
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; CHECK-NEXT: cmpne p1.h, p1/z, z2.h, #0
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; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
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; CHECK-NEXT: st1h { z0.h }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load volatile <64 x half>, ptr %a
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%op2 = load volatile <64 x half>, ptr %b
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%sel = select i1 %mask, <64 x half> %op1, <64 x half> %op2
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store <64 x half> %sel, ptr %a
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ret void
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}
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define void @select_v128f16(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 {
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; CHECK-LABEL: select_v128f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w2, #0x1
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; CHECK-NEXT: ptrue p0.h, vl128
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: mov z2.h, w8
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; CHECK-NEXT: and z2.h, z2.h, #0x1
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; CHECK-NEXT: cmpne p1.h, p1/z, z2.h, #0
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; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
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; CHECK-NEXT: st1h { z0.h }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load volatile <128 x half>, ptr %a
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%op2 = load volatile <128 x half>, ptr %b
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%sel = select i1 %mask, <128 x half> %op1, <128 x half> %op2
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store <128 x half> %sel, ptr %a
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ret void
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}
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; Don't use SVE for 64-bit vectors.
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define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, i1 %mask) vscale_range(2,0) #0 {
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; CHECK-LABEL: select_v2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: dup v2.2s, w8
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; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <2 x float> %op1, <2 x float> %op2
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ret <2 x float> %sel
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}
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; Don't use SVE for 128-bit vectors.
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define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, i1 %mask) vscale_range(2,0) #0 {
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; CHECK-LABEL: select_v4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: dup v2.4s, w8
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; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <4 x float> %op1, <4 x float> %op2
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ret <4 x float> %sel
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}
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define void @select_v8f32(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 {
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; CHECK-LABEL: select_v8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w2, #0x1
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; CHECK-NEXT: ptrue p0.s, vl8
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: mov z2.s, w8
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; CHECK-NEXT: cmpne p1.s, p1/z, z2.s, #0
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; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
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; CHECK-NEXT: st1w { z0.s }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load volatile <8 x float>, ptr %a
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%op2 = load volatile <8 x float>, ptr %b
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%sel = select i1 %mask, <8 x float> %op1, <8 x float> %op2
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store <8 x float> %sel, ptr %a
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ret void
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}
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define void @select_v16f32(ptr %a, ptr %b, i1 %mask) #0 {
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; VBITS_GE_256-LABEL: select_v16f32:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: mov x8, #8
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; VBITS_GE_256-NEXT: ptrue p0.s, vl8
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; VBITS_GE_256-NEXT: and w9, w2, #0x1
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; VBITS_GE_256-NEXT: ptrue p1.s
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; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]
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; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x1, x8, lsl #2]
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; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]
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; VBITS_GE_256-NEXT: mov z4.s, w9
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; VBITS_GE_256-NEXT: cmpne p1.s, p1/z, z4.s, #0
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; VBITS_GE_256-NEXT: sel z1.s, p1, z1.s, z3.s
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; VBITS_GE_256-NEXT: sel z0.s, p1, z0.s, z2.s
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; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]
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; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x0]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: select_v16f32:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: and w8, w2, #0x1
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; VBITS_GE_512-NEXT: ptrue p0.s, vl16
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; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]
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; VBITS_GE_512-NEXT: ptrue p1.s
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; VBITS_GE_512-NEXT: mov z2.s, w8
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; VBITS_GE_512-NEXT: cmpne p1.s, p1/z, z2.s, #0
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; VBITS_GE_512-NEXT: sel z0.s, p1, z0.s, z1.s
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; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x0]
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; VBITS_GE_512-NEXT: ret
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%op1 = load volatile <16 x float>, ptr %a
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%op2 = load volatile <16 x float>, ptr %b
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%sel = select i1 %mask, <16 x float> %op1, <16 x float> %op2
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store <16 x float> %sel, ptr %a
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ret void
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}
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define void @select_v32f32(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 {
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; CHECK-LABEL: select_v32f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w2, #0x1
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; CHECK-NEXT: ptrue p0.s, vl32
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: mov z2.s, w8
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; CHECK-NEXT: cmpne p1.s, p1/z, z2.s, #0
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; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
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; CHECK-NEXT: st1w { z0.s }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load volatile <32 x float>, ptr %a
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%op2 = load volatile <32 x float>, ptr %b
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%sel = select i1 %mask, <32 x float> %op1, <32 x float> %op2
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store <32 x float> %sel, ptr %a
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ret void
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}
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define void @select_v64f32(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 {
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; CHECK-LABEL: select_v64f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w2, #0x1
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; CHECK-NEXT: ptrue p0.s, vl64
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: mov z2.s, w8
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; CHECK-NEXT: cmpne p1.s, p1/z, z2.s, #0
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; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
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; CHECK-NEXT: st1w { z0.s }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load volatile <64 x float>, ptr %a
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%op2 = load volatile <64 x float>, ptr %b
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%sel = select i1 %mask, <64 x float> %op1, <64 x float> %op2
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store <64 x float> %sel, ptr %a
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ret void
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}
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; Don't use SVE for 64-bit vectors.
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define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, i1 %mask) vscale_range(2,0) #0 {
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; CHECK-LABEL: select_v1f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: csetm x8, ne
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; CHECK-NEXT: fmov d2, x8
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; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <1 x double> %op1, <1 x double> %op2
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ret <1 x double> %sel
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}
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; Don't use SVE for 128-bit vectors.
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define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, i1 %mask) vscale_range(2,0) #0 {
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; CHECK-LABEL: select_v2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: csetm x8, ne
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; CHECK-NEXT: dup v2.2d, x8
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; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%sel = select i1 %mask, <2 x double> %op1, <2 x double> %op2
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ret <2 x double> %sel
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}
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define void @select_v4f64(ptr %a, ptr %b, i1 %mask) vscale_range(2,0) #0 {
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; CHECK-LABEL: select_v4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w2, #0x1
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; CHECK-NEXT: ptrue p0.d, vl4
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: mov z2.d, x8
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; CHECK-NEXT: cmpne p1.d, p1/z, z2.d, #0
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; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
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; CHECK-NEXT: st1d { z0.d }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load volatile <4 x double>, ptr %a
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%op2 = load volatile <4 x double>, ptr %b
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%sel = select i1 %mask, <4 x double> %op1, <4 x double> %op2
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store <4 x double> %sel, ptr %a
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ret void
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}
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define void @select_v8f64(ptr %a, ptr %b, i1 %mask) #0 {
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; VBITS_GE_256-LABEL: select_v8f64:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: mov x8, #4
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; VBITS_GE_256-NEXT: ptrue p0.d, vl4
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; VBITS_GE_256-NEXT: and w9, w2, #0x1
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; VBITS_GE_256-NEXT: ptrue p1.d
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; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
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; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]
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; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x1, x8, lsl #3]
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; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]
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; VBITS_GE_256-NEXT: mov z4.d, x9
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; VBITS_GE_256-NEXT: cmpne p1.d, p1/z, z4.d, #0
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; VBITS_GE_256-NEXT: sel z1.d, p1, z1.d, z3.d
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; VBITS_GE_256-NEXT: sel z0.d, p1, z0.d, z2.d
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; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3]
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; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x0]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: select_v8f64:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: and w8, w2, #0x1
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; VBITS_GE_512-NEXT: ptrue p0.d, vl8
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; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
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|
; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]
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|
; VBITS_GE_512-NEXT: ptrue p1.d
|
|
; VBITS_GE_512-NEXT: mov z2.d, x8
|
|
; VBITS_GE_512-NEXT: cmpne p1.d, p1/z, z2.d, #0
|
|
; VBITS_GE_512-NEXT: sel z0.d, p1, z0.d, z1.d
|
|
; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x0]
|
|
; VBITS_GE_512-NEXT: ret
|
|
%op1 = load volatile <8 x double>, ptr %a
|
|
%op2 = load volatile <8 x double>, ptr %b
|
|
%sel = select i1 %mask, <8 x double> %op1, <8 x double> %op2
|
|
store <8 x double> %sel, ptr %a
|
|
ret void
|
|
}
|
|
|
|
define void @select_v16f64(ptr %a, ptr %b, i1 %mask) vscale_range(8,0) #0 {
|
|
; CHECK-LABEL: select_v16f64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: and w8, w2, #0x1
|
|
; CHECK-NEXT: ptrue p0.d, vl16
|
|
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]
|
|
; CHECK-NEXT: ptrue p1.d
|
|
; CHECK-NEXT: mov z2.d, x8
|
|
; CHECK-NEXT: cmpne p1.d, p1/z, z2.d, #0
|
|
; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
|
|
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load volatile <16 x double>, ptr %a
|
|
%op2 = load volatile <16 x double>, ptr %b
|
|
%sel = select i1 %mask, <16 x double> %op1, <16 x double> %op2
|
|
store <16 x double> %sel, ptr %a
|
|
ret void
|
|
}
|
|
|
|
define void @select_v32f64(ptr %a, ptr %b, i1 %mask) vscale_range(16,0) #0 {
|
|
; CHECK-LABEL: select_v32f64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: and w8, w2, #0x1
|
|
; CHECK-NEXT: ptrue p0.d, vl32
|
|
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]
|
|
; CHECK-NEXT: ptrue p1.d
|
|
; CHECK-NEXT: mov z2.d, x8
|
|
; CHECK-NEXT: cmpne p1.d, p1/z, z2.d, #0
|
|
; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
|
|
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load volatile <32 x double>, ptr %a
|
|
%op2 = load volatile <32 x double>, ptr %b
|
|
%sel = select i1 %mask, <32 x double> %op1, <32 x double> %op2
|
|
store <32 x double> %sel, ptr %a
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { "target-features"="+sve" }
|