forked from OSchip/llvm-project
66 lines
2.6 KiB
LLVM
66 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+aes -o - %s| FileCheck %s --check-prefixes=CHECK
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; Two operands are in scalar form.
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; Tests that both operands are loaded into SIMD registers directly as opposed to being loaded into GPR followed by a fmov.
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define void @test1(ptr %0, i64 %1, i64 %2) {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, x2, lsl #4
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; CHECK-NEXT: add x9, x0, x1, lsl #4
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; CHECK-NEXT: ldr d0, [x8, #8]
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; CHECK-NEXT: ldr d1, [x9, #8]
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; CHECK-NEXT: pmull v0.1q, v1.1d, v0.1d
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; CHECK-NEXT: str q0, [x0]
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; CHECK-NEXT: ret
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%4 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1
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%5 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1, i64 1
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%6 = load i64, ptr %5, align 8
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%7 = getelementptr inbounds <2 x i64>, ptr %0, i64 %2, i64 1
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%8 = load i64, ptr %7, align 8
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%9 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %6, i64 %8)
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store <16 x i8> %9, ptr %0, align 16
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ret void
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}
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; Operand %8 is higher-half of v2i64, and operand %7 is a scalar load.
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; Tests that operand is loaded into SIMD registers directly as opposed to being loaded into GPR followed by a fmov.
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define void @test2(ptr %0, i64 %1, i64 %2, <2 x i64> %3) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, x1, lsl #4
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; CHECK-NEXT: add x9, x8, #8
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; CHECK-NEXT: ld1r { v1.2d }, [x9]
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; CHECK-NEXT: pmull2 v0.1q, v0.2d, v1.2d
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; CHECK-NEXT: str q0, [x8]
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; CHECK-NEXT: ret
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%5 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1
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%6 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1, i64 1
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%7 = load i64, ptr %6, align 8
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%8 = extractelement <2 x i64> %3, i64 1
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%9 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %8, i64 %7)
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store <16 x i8> %9, ptr %5, align 16
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ret void
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}
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; Operand %7 is a scalar load, and operand %3 is an input parameter of function `test4`.
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; Test that %7 is loaded into SIMD registers.
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define void @test3(ptr %0, i64 %1, i64 %2, i64 %3) {
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; CHECK-LABEL: test3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, x1, lsl #4
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; CHECK-NEXT: fmov d0, x3
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; CHECK-NEXT: ldr d1, [x8, #8]
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; CHECK-NEXT: pmull v0.1q, v1.1d, v0.1d
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; CHECK-NEXT: str q0, [x8]
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; CHECK-NEXT: ret
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%5 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1
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%6 = getelementptr inbounds <2 x i64>, ptr %0, i64 %1, i64 1
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%7 = load i64, ptr %6, align 8
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%8 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %7, i64 %3)
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store <16 x i8> %8, ptr %5, align 16
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ret void
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}
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declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64)
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