forked from OSchip/llvm-project
41 lines
1.3 KiB
LLVM
41 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o -| FileCheck %s
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define <2 x i64> @test1(<4 x i32> %x) #0 {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, v0.s[1]
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; CHECK-NEXT: mov w9, v0.s[2]
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; CHECK-NEXT: fmov d0, x8
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; CHECK-NEXT: mov v0.d[1], x9
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; CHECK-NEXT: ret
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%i1 = extractelement <4 x i32> %x, i32 1
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%zi1 = zext i32 %i1 to i64
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%i2 = extractelement <4 x i32> %x, i32 2
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%zi2 = zext i32 %i2 to i64
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%v1 = insertelement <2 x i64> undef, i64 %zi1, i32 0
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%v2 = insertelement <2 x i64> %v1, i64 %zi2, i32 1
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ret <2 x i64> %v2
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}
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define <4 x i64> @test2(<4 x i32> %0) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, .LCPI1_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: mov w8, v0.s[1]
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; CHECK-NEXT: mov w9, v0.s[2]
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: mov v1.d[1], x9
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; CHECK-NEXT: ret
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entry:
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%1 = add <4 x i32> %0, <i32 -4, i32 -8, i32 -12, i32 -16>
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%2 = extractelement <4 x i32> %1, i32 1
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%zext1 = zext i32 %2 to i64
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%3 = extractelement <4 x i32> %1, i32 2
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%zext2 = zext i32 %3 to i64
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%4 = insertelement <4 x i64> undef, i64 %zext1, i32 2
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%5 = insertelement <4 x i64> %4, i64 %zext2, i32 3
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ret <4 x i64> %5
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}
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