forked from OSchip/llvm-project
[AArch64] Regenerate arm64-mul.ll test checks
This commit is contained in:
Simon Pilgrim
parent
3dccac09a6
commit
ccc2a60bc8
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@ -1,13 +1,17 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
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; rdar://9296808
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; rdar://9349137
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define i128 @t1(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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; CHECK: umulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mul x8, x0, x1
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; CHECK-NEXT: umulh x1, x0, x1
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; CHECK-NEXT: mov x0, x8
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; CHECK-NEXT: ret
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entry:
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%tmp1 = zext i64 %a to i128
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%tmp2 = zext i64 %b to i128
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%tmp3 = mul i128 %tmp1, %tmp2
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@ -15,10 +19,13 @@ entry:
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}
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define i128 @t2(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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; CHECK: smulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mul x8, x0, x1
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; CHECK-NEXT: smulh x1, x0, x1
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; CHECK-NEXT: mov x0, x8
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; CHECK-NEXT: ret
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entry:
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%tmp1 = sext i64 %a to i128
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%tmp2 = sext i64 %b to i128
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%tmp3 = mul i128 %tmp1, %tmp2
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@ -26,9 +33,11 @@ entry:
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}
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define i64 @t3(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK-LABEL: t3:
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; CHECK: umull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: umull x0, w0, w1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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@ -36,9 +45,11 @@ entry:
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}
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define i64 @t4(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK-LABEL: t4:
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; CHECK: smull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: smull x0, w0, w1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = sext i32 %a to i64
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%tmp2 = sext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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@ -46,9 +57,11 @@ entry:
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}
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define i64 @t5(i32 %a, i32 %b, i64 %c) nounwind {
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entry:
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; CHECK-LABEL: t5:
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; CHECK: umaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: umaddl x0, w0, w1, x2
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; CHECK-NEXT: ret
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entry:
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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@ -57,9 +70,11 @@ entry:
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}
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define i64 @t6(i32 %a, i32 %b, i64 %c) nounwind {
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entry:
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; CHECK-LABEL: t6:
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; CHECK: smsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: smsubl x0, w0, w1, x2
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; CHECK-NEXT: ret
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entry:
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%tmp1 = sext i32 %a to i64
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%tmp2 = sext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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@ -68,9 +83,11 @@ entry:
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}
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define i64 @t7(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK-LABEL: t7:
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; CHECK: umnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: umnegl x0, w0, w1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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@ -79,9 +96,11 @@ entry:
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}
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define i64 @t8(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK-LABEL: t8:
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; CHECK: smnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: smnegl x0, w0, w1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = sext i32 %a to i64
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%tmp2 = sext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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@ -90,9 +109,13 @@ entry:
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}
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define i64 @t9(i32 %a) nounwind {
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entry:
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; CHECK-LABEL: t9:
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; CHECK: umull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #8896
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; CHECK-NEXT: movk w8, #2, lsl #16
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; CHECK-NEXT: umull x0, w0, w8
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; CHECK-NEXT: ret
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entry:
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%tmp1 = zext i32 %a to i64
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%tmp2 = mul i64 %tmp1, 139968
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ret i64 %tmp2
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@ -100,9 +123,15 @@ entry:
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; Check 64-bit multiplication is used for constants > 32 bits.
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define i64 @t10(i32 %a) nounwind {
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entry:
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; CHECK-LABEL: t10:
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; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #2
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: sxtw x9, w0
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; CHECK-NEXT: movk w8, #32768, lsl #16
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; CHECK-NEXT: mul x0, x9, x8
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; CHECK-NEXT: ret
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entry:
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%tmp1 = sext i32 %a to i64
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%tmp2 = mul i64 %tmp1, 2147483650 ; = 2^31 + 2
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ret i64 %tmp2
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@ -110,9 +139,13 @@ entry:
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; Check the sext_inreg case.
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define i64 @t11(i64 %a) nounwind {
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entry:
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; CHECK-LABEL: t11:
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; CHECK: smnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #29594
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; CHECK-NEXT: movk w8, #65499, lsl #16
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; CHECK-NEXT: smnegl x0, w0, w8
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; CHECK-NEXT: ret
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entry:
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%tmp1 = trunc i64 %a to i32
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%tmp2 = sext i32 %tmp1 to i64
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%tmp3 = mul i64 %tmp2, -2395238
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@ -121,9 +154,13 @@ entry:
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}
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define i64 @t12(i64 %a, i64 %b) nounwind {
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entry:
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; CHECK-LABEL: t12:
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; CHECK: smaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #35118
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; CHECK-NEXT: movk w8, #65008, lsl #16
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; CHECK-NEXT: smaddl x0, w0, w8, x1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = trunc i64 %a to i32
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%tmp2 = sext i32 %tmp1 to i64
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%tmp3 = mul i64 %tmp2, -34567890
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@ -132,9 +169,13 @@ entry:
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}
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define i64 @t13(i32 %a, i64 %b) nounwind {
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entry:
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; CHECK-LABEL: t13:
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; CHECK: umsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #24910
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; CHECK-NEXT: movk w8, #188, lsl #16
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; CHECK-NEXT: umsubl x0, w0, w8, x1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = zext i32 %a to i64
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%tmp3 = mul i64 %tmp1, 12345678
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%tmp4 = sub i64 %b, %tmp3
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@ -142,9 +183,13 @@ entry:
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}
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define i64 @t14(i32 %a, i64 %b) nounwind {
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entry:
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; CHECK-LABEL: t14:
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; CHECK: smsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #40626
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; CHECK-NEXT: movk w8, #65347, lsl #16
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; CHECK-NEXT: smsubl x0, w0, w8, x1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = sext i32 %a to i64
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%tmp3 = mul i64 %tmp1, -12345678
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%tmp4 = sub i64 %b, %tmp3
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