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SpinalDoc-RTD
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Fix uart dataLength = 8

This commit is contained in:
Dolu1990 2024-10-14 09:33:05 +02:00
parent d379dd613e
commit fee0edfd28
1 changed files with 4 additions and 4 deletions
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8
examples/src/main/scala/spinaldoc/examples/intermediate/Uart.scala
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@ -345,7 +345,7 @@ case class UartRxTx() extends Component {
val uartCtrl = UartCtrl( val uartCtrl = UartCtrl(
config=UartCtrlInitConfig( config=UartCtrlInitConfig(
baudrate = 115200, baudrate = 115200,
dataLength = 8, dataLength = 7,
parity = UartParityType.NONE, parity = UartParityType.NONE,
stop = UartStopType.ONE stop = UartStopType.ONE
) )
@ -365,7 +365,7 @@ case class UartTx() extends Component {
val uartCtrl = UartCtrl( val uartCtrl = UartCtrl(
config=UartCtrlInitConfig( config=UartCtrlInitConfig(
baudrate = 115200, baudrate = 115200,
dataLength = 8, dataLength = 7,
parity = UartParityType.NONE, parity = UartParityType.NONE,
stop = UartStopType.ONE stop = UartStopType.ONE
) )
@ -386,7 +386,7 @@ case class UartRx() extends Component {
val uartCtrl = UartCtrl( val uartCtrl = UartCtrl(
config = UartCtrlInitConfig( config = UartCtrlInitConfig(
baudrate = 115200, baudrate = 115200,
dataLength = 8, dataLength = 7,
parity = UartParityType.NONE, parity = UartParityType.NONE,
stop = UartStopType.ONE stop = UartStopType.ONE
), ),
@ -467,7 +467,7 @@ case class UartWithHeader() extends Component {
val uartCtrl = UartCtrl( val uartCtrl = UartCtrl(
config=UartCtrlInitConfig( config=UartCtrlInitConfig(
baudrate = 115200, baudrate = 115200,
dataLength = 8, dataLength = 7,
parity = UartParityType.NONE, parity = UartParityType.NONE,
stop = UartStopType.ONE stop = UartStopType.ONE
) )