Commit Graph

1371 Commits

Author SHA1 Message Date
Javed Absar 1f8a87749f [ARM] Fix Neon vector type alignment to 64-bit
This is restricted version of patch - https://reviews.llvm.org/D33205
that I reverted as it was leading to ABI breaks on darwin etc.
This patch restricts the fix to AAPCS (Android remains 128-bit).
Reviewed by: Renato Golin, Stephen Hines
Differential Revision: https://reviews.llvm.org/D33786



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304889 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-07 10:02:02 +00:00
Dan Gohman 260b4fb81b [WebAssembly] Set MaxAtomicInlineWidth to 64.
The WebAssembly threads proposal has changed such that C++
implementations can now declare that atomics up to 64 bits are
"lock free" in C++'s terms.


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304859 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-07 02:22:40 +00:00
Florian Hahn 84aa45a35c [ARM] Add support for target("arm") and target("thumb").
Summary:
This patch adds support for the target("arm") and target("thumb")
attributes, which can be used to force the compiler to generated ARM or
Thumb code for a function.

In LLVM, ARM or Thumb code generation can be controlled by the
thumb-mode target feature. But GCC already uses target("arm") and
target("thumb"), so we have to substitute "arm" with -thumb-mode and
"thumb" with +thumb-mode.


Reviewers: echristo, pcc, kristof.beyls

Reviewed By: echristo

Subscribers: ahatanak, aemerson, javed.absar, kristof.beyls, cfe-commits

Differential Revision: https://reviews.llvm.org/D33721

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304781 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-06 09:26:15 +00:00
Vedant Kumar d4d74154eb Revert "[AArch64] Add ARMv8.2-A FP16 vefctor intrinsics"
This reverts commit r304493. It breaks all the Darwin bots:
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental_check/37168

Failure:
Failing Tests (2):
    Clang :: CodeGen/aarch64-v8.2a-neon-intrinsics.c
    Clang :: CodeGen/arm_neon_intrinsics.c

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304509 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 01:22:14 +00:00
Abderrazek Zaafrani d751aefbc7 [AArch64] Add ARMv8.2-A FP16 vefctor intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304493 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-01 23:22:29 +00:00
Pekka Jaaskelainen 140f5e804c [OpenCL] Makes kernels use the SPIR_KERNEL CC by default.
Rationale: OpenCL kernels are called via an explicit runtime API
with arguments set with clSetKernelArg(), not as normal sub-functions.
Return SPIR_KERNEL by default as the kernel calling convention to ensure
the fingerprint is fixed such way that each OpenCL argument gets one
matching argument in the produced kernel function argument list to enable
feasible implementation of clSetKernelArg() with aggregates etc. In case
we would use the default C calling conv here, clSetKernelArg() might
break depending on the target-specific conventions; different targets
might split structs passed as values to multiple function arguments etc.

https://reviews.llvm.org/D33639



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304389 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-01 07:18:49 +00:00
Javed Absar a841e133b3 Reverting Neon vector type 64-alignment fix
The patch caused ABI breaks on darwin/others.
Reverting to come back with a more restrictive patch.



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304220 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-30 17:09:47 +00:00
Javed Absar 14af789730 [ARM] Fix Neon vector type alignment to 64-bit
The maximum alignment for ARM NEON data types should be 64-bits as specified
in ARM procedure call standard document Sec. A.2 Notes.
This patch fixes it from its current larger natural default values, except
for Android (so as not to break existing ABI).
Reviewed by: Stephen Hines, Renato Golin.
Differential Revision: https://reviews.llvm.org/D33205



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304201 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-30 10:12:15 +00:00
Reid Kleckner e825648552 Only define __SIZEOF_FLOAT128__ on x86 as intended in r304012
GCC only defines it on x86.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304013 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-26 17:48:01 +00:00
Reid Kleckner b123c46f72 Enable __float128 for mingw for GCC compatibility and define __SIZEOF_FLOAT128__ on x86
GCC defines __FLOAT128__ on Power and __SIZEOF_FLOAT128__ on x86. We're
just following the inconsistency for now so users have some way to test.

Effectively merges this patch as requested by Martell Malone:
https://github.com/Alexpux/MINGW-packages/blob/master/mingw-w64-clang/0107-enable-__float128-for-X86-MinGW.patch

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304012 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-26 17:38:15 +00:00
Oren Ben Simhon 0197dcf96b [X86] Adding avx512_vpopcntdq feature set and its intrinsics
AVX512_VPOPCNTDQ is a new feature set that was published by Intel.
The patch represents the Clang side of the addition of six intrinsics for two new machine instructions (vpopcntd and vpopcntq).
It also includes the addition of the new feature set.

Differential Revision: https://reviews.llvm.org/D33170



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@303857 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 13:44:11 +00:00
Saleem Abdulrasool 5497518e68 Basic: fix whitespace in file header (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@303804 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 20:27:09 +00:00
Galina Kistanova 0cb0ba2898 Removed fallthrough annotation which does not directly precede switch label.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@303653 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-23 16:56:10 +00:00
Galina Kistanova 022c4ea26e Added LLVM_FALLTHROUGH to address gcc warning: this statement may fall through.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@303649 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-23 16:33:07 +00:00
Yaxun Liu 5bd539fd3e [AMDGPU] Do not require opencl triple environment for OpenCL
A recent change requires opencl triple environment for compiling OpenCL
program, which causes regressions in libclc.

This patch fixes that. Instead of deducing language based on triple
environment, it checks LangOptions.

Differential Revision: https://reviews.llvm.org/D33445


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@303644 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-23 16:15:53 +00:00
Yaxun Liu 3022dac388 CodeGen: Cast alloca to expected address space
Alloca always returns a pointer in alloca address space, which may
be different from the type defined by the language. For example,
in C++ the auto variables are in the default address space. Therefore
cast alloca to the expected address space when necessary.

Differential Revision: https://reviews.llvm.org/D32248


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@303370 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-18 18:51:09 +00:00
James Y Knight e92a9a577b [SPARC] Support 'f' and 'e' inline asm constraints.
Patch by Patrick Boettcher.

Differential Revision: https://reviews.llvm.org/D29117

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@302913 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-12 16:01:23 +00:00
Simon Pilgrim a7c6c642e3 [X86][LWP] Add clang support for LWP instructions.
This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4).

Differential Revision: https://reviews.llvm.org/D32770

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@302418 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 12:09:45 +00:00
Weiming Zhao e862caa270 [ARM] Limit the diagnose when an ISR calls a regular function
Summary:
When the function is compiled with soft-float or on CPU with no FPU, we
don't need to diagnose for a call from an ISR to a regular function.

Reviewers: jroelofs, eli.friedman

Reviewed By: jroelofs

Subscribers: aemerson, rengolin, javed.absar, cfe-commits

Differential Revision: https://reviews.llvm.org/D32918

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@302274 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-05 19:25:29 +00:00
Duncan P. N. Exon Smith 6b7fb45df3 Darwin: Define __STDC_NO_THREADS__ on Darwin targets
Darwin doesn't support C11 threads.h.  Define `__STDC_NO_THREADS__` so
that users can check for it.

rdar://problem/18461003

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@301508 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-27 01:47:22 +00:00
Oliver Stannard 91aca438d2 [ARM,AArch64] Define __ELF__ for arm-none-eabihf and AArch64
This macro is defined for arm-none-eabi as of r266625, but it should also be
defined for eabihf and aarch64.



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@300549 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-18 13:12:36 +00:00
Eric Christopher b57bc56b77 When we turn on vsx it should also turn on altivec explicitly, same
with disabling it as well as disabling all vsx specific features when
turning off altivec.

Fixes PR32663.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@300395 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-15 06:15:00 +00:00
Konstantin Zhuravlyov 5325399c14 [AMDGPU][GFX9] Set +fp32-denormals for >=gfx900 unless -cl-denorms-are-zero is set
Differential Revision: https://reviews.llvm.org/D31482


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@300306 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-14 05:33:57 +00:00
Yaxun Liu 44e7dd4bbb [OpenCL] Map default address space to alloca address space
For OpenCL, the private address space qualifier is 0 in AST. Before this change, 0 address space qualifier
is always mapped to target address space 0. As now target private address space is specified by
alloca address space in data layout, address space qualifier 0 needs to be mapped to alloca addr space specified by the data layout.

This change has no impact on targets whose alloca addr space is 0.

With contributions from Matt Arsenault, Tony Tye and Wen-Heng (Jack) Chung

Differential Revision: https://reviews.llvm.org/D31404


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@299965 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-11 17:24:23 +00:00
Yaxun Liu e7bf9bd23e [AMDGPU] Temporarily change constant address space from 4 to 2 for the new address space mapping
Change constant address space from 4 to 2 for the new address space mapping in Clang.

Differential Revision: https://reviews.llvm.org/D31771


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@299691 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 19:18:36 +00:00
Eric Christopher d4fc66ef14 Default enable the rtm feature only on skylake and later for now because Intel disabled the feature on some haswell and broadwell processors:
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf

the -mrtm option will still work normally.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298956 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-28 23:03:19 +00:00
Eric Christopher ff19b51066 _CALL_LINUX is only defined on 64-bit ppc linux platforms, not 32-bit.
Adjust and add a test for the 32-bit side.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298778 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-25 19:26:04 +00:00
Yaxun Liu c1eaf2a7e2 [AMDGPU] Make AMDGPUTargetInfo::AS private
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298773 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-25 11:34:41 +00:00
Eric Christopher ec06c1d2ef Update the comment on not yet generated preprocessor defines to remove __LONGDOUBLE128.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298771 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-25 06:38:57 +00:00
Eric Christopher 3896b8c2cc Add the __LONGDOUBLE128 define for ppc targets that have 128 bit long doubles.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298770 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-25 06:37:23 +00:00
Eric Christopher 7e7626a7ef Define __HAVE_BSWAP__ on ppc to match gcc since we support both builtins as well.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298769 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-25 05:40:13 +00:00
Yaxun Liu d939951427 [AMDGPU] Switch address space mapping by triple environment amdgiz
For target environment amdgiz and amdgizcl (giz means Generic Is Zero), AMDGPU will use new address space mapping where generic address space is 0 and private address space is 5. The data layout is also changed correspondingly.

Differential Revision: https://reviews.llvm.org/D31210


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298767 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-25 03:46:25 +00:00
Eric Christopher 9950a2ccb2 Add the _CALL_LINUX preprocessor define for ppc linux platforms.
This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but
our ppc suppport post-dates this and it should work on all linux platforms. It
is guaranteed to work on all elfv2 platforms.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298765 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-25 03:33:59 +00:00
Eric Christopher 6a69439a01 __BIGGEST_ALIGNMENT__ has always been 16 on all power platforms rather
than the default of 8 in clang, fix and update tests accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298761 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-25 02:55:21 +00:00
Eric Christopher 949f2b188e Add preprocessor defines for a bare powerpc64le triple/cpu.
The le triple didn't exist until power8, so use that as a default (this
also matches what gcc does).

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298759 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-25 02:29:18 +00:00
Eric Christopher 9a1877f04c Move setting of LangOpts based on target flags out of CompilerInstance
and into TargetInfo::adjust so that it gets called in more places
throughout the compiler (AST serialization in particular).

Should fix PPC modules after removing of faltivec.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298487 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-22 06:36:09 +00:00
Eric Christopher a776ed1122 Remove the -faltivec alias option and replace it with -maltivec everywhere.
The alias was only ever used on darwin and had some issues there,
and isn't used in practice much. Also fixes a problem with -mno-altivec
not turning off -maltivec.

Also add a diagnostic for faltivec/fno-altivec that directs users to use
maltivec options and include the altivec.h file explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298449 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-21 22:06:18 +00:00
Eric Christopher 9bdc71fb93 Turn on HTM on power8 and later (including powerpc64le) since it's
available by default on those cpus and configurations.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298307 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-20 21:12:53 +00:00
Krzysztof Parzyszek 955221a189 [Hexagon] Recognize hexagonv62 as a valid target CPU
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@297778 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-14 20:29:23 +00:00
Matt Arsenault 55175b19fc AMDGPU: Make 0 the private nullptr value
We can't actually pretend that 0 is valid for address space 0.
r295877 added a workaround to stop allocating user objects
there, so we can use 0 as the invalid pointer.

Some of the tests seemed to be using private as the non-0 null
test address space, so add copies using local to make sure
this is still stressed.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@297659 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-13 19:47:53 +00:00
Yaxun Liu 7679a84815 [AMDGPU] Add builtin functions readlane ds_permute mov_dpp
Differential Revision: https://reviews.llvm.org/D30551


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@297436 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-10 01:30:46 +00:00
Konstantin Zhuravlyov ade7b0f6d9 [DebugInfo] Add address space when creating DIDerivedTypes
Differential Revision: https://reviews.llvm.org/D29671


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@297321 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-08 23:56:48 +00:00
Brad Smith c3ef9530ae Set the Int64Type / IntMaxType types correctly for OpenBSD/mips64
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@297098 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-06 23:48:31 +00:00
Eric Christopher 582508d19a Migrate all of aarch64-linux-gnu to \01_mcount instead of just when passing along gnueabi as this matches both gcc and what the kernel expects.
More of PR27311

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@296490 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-28 17:22:05 +00:00
Brad Smith b144ec9ca3 Set ABIs correctly for OpenBSD/arm; soft float and aapcs-linux.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@296430 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-28 03:20:26 +00:00
Matt Arsenault 521e2b23fa AMDGPU: Add fmed3 half builtin
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@295874 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 20:55:59 +00:00
Brad Smith dde2824b64 Hook up OpenBSD AArch64 support
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@295786 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-21 23:13:09 +00:00
Simon Dardis b3210f2343 [mips] Define macros related to -mabicalls in the preprocessor
Summary:
Historically, NetBSD, FreeBSD and OpenBSD have defined the macro ABICALLS in
the preprocessor when -mabicalls is in effect.

Mainline GCC later defined __mips_abicalls when -mabicalls is in effect.

This patch teaches the preprocessor to define these macros when appropriate.

NetBSD does not require the ABICALLS macro.

This resolves PR/31694.

Thanks to Sean Bruno for highlighting this issue!

Reviewers: slthakur, seanbruno

Reviewed By: seanbruno

Subscribers: joerg, brad, emaste, seanbruno, cfe-commits

Differential Revision: https://reviews.llvm.org/D29032



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@295728 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-21 16:01:00 +00:00
Brad Smith 571d97eea4 Enable support for __float128 in Clang on OpenBSD/X86
/usr/local/include/c++/4.9.4/type_traits:279:39: error: __float128 is not
supported on this target


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@295635 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-20 03:18:15 +00:00
Matt Arsenault f33af75ca7 AMDGPU: Add gfx900 and gfx901 processors
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@295556 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 19:02:41 +00:00