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[ARM] Fix Neon vector type alignment to 64-bit 

This is restricted version of patch - https://reviews.llvm.org/D33205
that I reverted as it was leading to ABI breaks on darwin etc.
This patch restricts the fix to AAPCS (Android remains 128-bit).
Reviewed by: Renato Golin, Stephen Hines
Differential Revision: https://reviews.llvm.org/D33786



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304889 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Javed Absar 2017-06-07 10:02:02 +00:00
parent 98df4e7a69
commit 1f8a87749f
2 changed files with 21 additions and 0 deletions
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4
lib/Basic/Targets.cpp
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@ -5385,6 +5385,10 @@ public:
// ARM has atomics up to 8 bytes
setAtomic();
// Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android))
MaxVectorAlign = 64;
// Do force alignment of members that follow zero length bitfields. If
// the alignment of the zero-length bitfield is greater than the member
// that follows it, `bar', `bar' will be aligned as the type of the

17
test/CodeGen/neon-aapcs-align.c Normal file
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@ -0,0 +1,17 @@
// RUN: %clang_cc1 -triple armv7a-none-eabi -target-feature +neon -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=AAPCS
// RUN: %clang_cc1 -triple armv7a-none-gnueabi -target-feature +neon -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=AAPCS
// RUN: %clang_cc1 -triple armv7a-none-freebsd -target-feature +neon -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=AAPCS
// RUN: %clang_cc1 -triple armv7a-apple-ios -target-feature +neon -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=DEFAULT
// RUN: %clang_cc1 -triple armv7a-none-android -target-feature +neon -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=DEFAULT
// RUN: %clang_cc1 -triple armv7a-none-androideabi -target-feature +neon -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=DEFAULT
#include <arm_neon.h>
// Neon types have 64-bit alignment
int32x4_t gl_b;
void t3(int32x4_t *src) {
// CHECK: @t3
gl_b = *src;
// AAPCS: store <4 x i32> {{%.*}}, <4 x i32>* @gl_b, align 8
// DEFAULT: store <4 x i32> {{%.*}}, <4 x i32>* @gl_b, align 16
}